From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B612F30C156 for ; Sat, 25 Jul 2026 05:12:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784956324; cv=none; b=h2msgYsnnBzDifajgaakrtCI+D6njV/qaWf8l8yh2CcxI5qMUlSeomf7HrX+NEGLkP5qgkfBFCRmYyX4QmioHkCS2hJcEVs7Xi9rFBZ8qgk0go0nqTirRBvKJqYdjiWEtJCPhGSEIIO/dkeqIdCARqVaqsoTl5ku3LQr674Cfy0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784956324; c=relaxed/simple; bh=nZrUS3odbqXIAtcS6DhX7YljHg34q1r7SmoISnltkB8=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=F66pg510CsH0tTjgZLQ4rP1KziL1y4872Gwba2k1fjU7eDxhfcbf4tVwPMWYmCzz6kiwHkGsM98oWs0Zqbp3gm0jZNMBNQOmyV7rdEtDvthXk2R9ieNBDAKmBmcXfVhfqy1mysS/1/PMbn6phXgULETsK8pxB0RQG3SP5NoMfS4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Xape2hWe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Xape2hWe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C64D01F000E9; Sat, 25 Jul 2026 05:12:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784956323; bh=zfDIe0jTVWLaFGOUrSraY+Ff1wIleInx4p1re0OCiRI=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Xape2hWexNPq6GbnmbuuCpBIQ2DGvKC4NPtjqhCIr6sQsOQQjifP2pXjoIvWwtAGN CYWK2zEB+9uWmJiEXShV8tkH2hnXHDmpj0dgJZXN3sMU8D6SE7NBPEXogY1emgEVIj A0WJJxSKYrAJstAOMUGbDdi54GR7rfjPV5C1k4hgg2PeeWawf1AS1PRMvfmjMtPUvD YMRX+B2oU5PUa3ko2dPPSoJoJfzOokUIT4igmwqXuUmO0ivk884ZDkoJ5TSHLtm/UR H4vWrSFdnjU0SUB5wkWNARBhr3Sxm8XtObk12ki8Ro98MZjIEInor5YHCLuY0QD2Kj KEkKzD5mdI5Mg== From: sashiko-bot@kernel.org Subject: Re: [PATCH RESEND 15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output Reply-To: sashiko-reviews@lists.linux.dev To: "Cody Kang" Cc: vkoul@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, olteanv@gmail.com, neil.armstrong@linaro.org, linux-phy@lists.infradead.org, robh@kernel.org, conor+dt@kernel.org In-Reply-To: <20260725-k3-display-v1-15-6de34d80e86c@gmail.com> References: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> <20260725-k3-display-v1-15-6de34d80e86c@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Sat, 25 Jul 2026 05:12:02 +0000 Message-Id: <20260725051202.C64D01F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 2 potential issue(= s) to consider: - [High] Precision Loss in DP Timing Configuration due to integer division - [High] Protocol Violation in I2C-over-AUX EDID Read (Missing MOT flag) -- --- Patch [15]: [PATCH RESEND 15/17] riscv: dts: spacemit: k3-pico-itx: ena= ble the DisplayPort output --- commit 8521347c30ea3dc057bb9d8b08c1de584bd6ba67 Author: Cody Kang riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output This commit enables the second Saturn DPU and the corresponding DisplayPort controller on the Pico-ITX board. While this patch configures the devicetree to route the DPU output, it exposes regressions in the newly added underlyi= ng Innosilicon DP/eDP driver. > diff --git a/drivers/gpu/drm/spacemit/spacemit_inno_dp.c b/drivers/gpu/dr= m/spacemit/spacemit_inno_dp.c > new file mode 100644 > --- /dev/null > +++ b/drivers/gpu/drm/spacemit/spacemit_inno_dp.c [ ... ] > @@ -982,19 +982,19 @@ static void spacemit_dp_hw_set_msa_and_enable_video= (struct spacemit_dp_dev *dp, > const struct drm_display_mode *mode, > enum spacemit_dp_link_rate rate, > enum spacemit_dp_lane_count lanes, > u32 color_format) > { > u64 hb_num; > u32 link_rate; > u32 fp; /* Pixel clock in MHz */ > u32 bpp, misc0; > u32 tu, tu_frac, tu_int, rd_thres; > u32 hsync_len; > =20 > /* mode->clock unit is kHz, fp unit is MHz */ > if (dp->use_ext_pixel_clock) > fp =3D dp->pixel_clock / 1000; > else > fp =3D mode->clock / 1000; > =20 > if (fp =3D=3D 0) > fp =3D 1; /* Prevent division by zero */ [Severity: High] Will dividing by 1000 here truncate necessary precision? Since mode->clock / 1000 discards the fractional part (for example, a 74.25 MHz clock becomes 74 MHz), this truncated value is used in calculating the Transfer Unit size and horizontal blanking interval. This discrepancy can cause the display controller and the DP transmitter to disagree on the required bandwidth, resulting in the DP TX FIFO overflowing and corrupting the display for common standard resolutions like 720p and 1080p. [ ... ] > @@ -1278,9 +1278,9 @@ static int spacemit_dp_aux_i2c_write(struct spacemi= t_dp_dev *dp, u32 address, > const u8 *buf, size_t len) > { > struct drm_dp_aux_msg msg =3D { > .address =3D address, > .request =3D DP_AUX_I2C_WRITE, [Severity: High] Is it intentional to hardcode DP_AUX_I2C_WRITE here without allowing the DP_AUX_I2C_MOT (Middle Of Transaction) flag to be appended? [ ... ] > @@ -1320,11 +1320,11 @@ static int spacemit_dp_conn_get_edid_block(void *= data, u8 *buf, > int ret, retry; > size_t offset; > =20 > if (segment) { > for (retry =3D 0; retry < 3; retry++) { > ret =3D spacemit_dp_aux_i2c_write(dp, > SPACEMIT_DP_DDC_SEGMENT_ADDR, &segment, 1); > if (!ret) > break; > } [Severity: High] Can this segment write cause the hardware to generate an I2C STOP condition? Because spacemit_dp_aux_i2c_write() lacks the MOT flag, writing the E-DDC segment pointer without it directs the hardware to generate a STOP conditio= n. According to the E-DDC specification, a STOP condition immediately after writing the segment pointer forces the display EEPROM to reset its segment pointer to 0. As a result, subsequent reads might always fetch EDID blocks 0 and 1, making it impossible to correctly read EDID blocks >=3D 2 (such as CTA-861 extensi= on blocks) and potentially breaking support for advanced resolutions and audio and HDR features. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260725-k3-display= -v1-0-6de34d80e86c@gmail.com?part=3D15 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62B55C531C9 for ; Sat, 25 Jul 2026 05:12:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4LeMzJSEB5PPF7c+iH6+fy+MWUyIYh2XT1aYuVFRBvA=; b=zxQRz0rFmpBBwU FEUzd+kcxoe9zktJIV2K4JMgcTGnYCJ2gc8NCo/UD0HaaEeSlBqnk/JXw2jZWCJUj5vAycQFXi49v SKz0Wu4fKFK5MGUit+k02EVXPS8q1lePekprzcSCn500leE5GtXWWpcwWNjLUJxSXmOWp9uOM8OLi U2Y3Uyj786jo4PzwUPDHXYVbRn2Q7/M0f65gOWGOfLvZHerDvJG1WC7wcQ8scc6c81pc9zTkhSRkv nharPBwKtylGUDedrqJ6Wrbmi5OU2Ac9E6ki+KC7BLOEnjBXbf9Fi0RA+8KoFTr8YPLh0wMZ0KlvO x5zITp4FMNzmgVUuJ8Aw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wnUg9-000000003ON-0G80; Sat, 25 Jul 2026 05:12:05 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wnUg7-000000003OB-3ZRs for linux-phy@lists.infradead.org; Sat, 25 Jul 2026 05:12:03 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 6880E42D53; Sat, 25 Jul 2026 05:12:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C64D01F000E9; Sat, 25 Jul 2026 05:12:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784956323; bh=zfDIe0jTVWLaFGOUrSraY+Ff1wIleInx4p1re0OCiRI=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Xape2hWexNPq6GbnmbuuCpBIQ2DGvKC4NPtjqhCIr6sQsOQQjifP2pXjoIvWwtAGN CYWK2zEB+9uWmJiEXShV8tkH2hnXHDmpj0dgJZXN3sMU8D6SE7NBPEXogY1emgEVIj A0WJJxSKYrAJstAOMUGbDdi54GR7rfjPV5C1k4hgg2PeeWawf1AS1PRMvfmjMtPUvD YMRX+B2oU5PUa3ko2dPPSoJoJfzOokUIT4igmwqXuUmO0ivk884ZDkoJ5TSHLtm/UR H4vWrSFdnjU0SUB5wkWNARBhr3Sxm8XtObk12ki8Ro98MZjIEInor5YHCLuY0QD2Kj KEkKzD5mdI5Mg== From: sashiko-bot@kernel.org Subject: Re: [PATCH RESEND 15/17] riscv: dts: spacemit: k3-pico-itx: enable the DisplayPort output To: "Cody Kang" Cc: vkoul@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, olteanv@gmail.com, neil.armstrong@linaro.org, linux-phy@lists.infradead.org, robh@kernel.org, conor+dt@kernel.org In-Reply-To: <20260725-k3-display-v1-15-6de34d80e86c@gmail.com> References: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> <20260725-k3-display-v1-15-6de34d80e86c@gmail.com> Date: Sat, 25 Jul 2026 05:12:02 +0000 Message-Id: <20260725051202.C64D01F000E9@smtp.kernel.org> X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MiBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIFByZWNpc2lvbiBMb3Nz IGluIERQIFRpbWluZyBDb25maWd1cmF0aW9uIGR1ZSB0byBpbnRlZ2VyIGRpdmlzaW9uCi0gW0hp Z2hdIFByb3RvY29sIFZpb2xhdGlvbiBpbiBJMkMtb3Zlci1BVVggRURJRCBSZWFkIChNaXNzaW5n IE1PVCBmbGFnKQotLQoKLS0tIFBhdGNoIFsxNV06IFtQQVRDSCBSRVNFTkQgMTUvMTddIHJpc2N2 OiBkdHM6IHNwYWNlbWl0OiBrMy1waWNvLWl0eDogZW5hYmxlIHRoZSBEaXNwbGF5UG9ydCBvdXRw dXQgLS0tCmNvbW1pdCA4NTIxMzQ3YzMwZWEzZGMwNTdiYjlkOGIwOGMxZGU1ODRiZDZiYTY3CkF1 dGhvcjogQ29keSBLYW5nIDxjb2R5a2FuZy5oa0BnbWFpbC5jb20+CgpyaXNjdjogZHRzOiBzcGFj ZW1pdDogazMtcGljby1pdHg6IGVuYWJsZSB0aGUgRGlzcGxheVBvcnQgb3V0cHV0CgpUaGlzIGNv bW1pdCBlbmFibGVzIHRoZSBzZWNvbmQgU2F0dXJuIERQVSBhbmQgdGhlIGNvcnJlc3BvbmRpbmcg RGlzcGxheVBvcnQKY29udHJvbGxlciBvbiB0aGUgUGljby1JVFggYm9hcmQuIFdoaWxlIHRoaXMg cGF0Y2ggY29uZmlndXJlcyB0aGUgZGV2aWNldHJlZQp0byByb3V0ZSB0aGUgRFBVIG91dHB1dCwg aXQgZXhwb3NlcyByZWdyZXNzaW9ucyBpbiB0aGUgbmV3bHkgYWRkZWQgdW5kZXJseWluZwpJbm5v c2lsaWNvbiBEUC9lRFAgZHJpdmVyLgoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3Nw YWNlbWl0L3NwYWNlbWl0X2lubm9fZHAuYyBiL2RyaXZlcnMvZ3B1L2RybS9zcGFjZW1pdC9zcGFj ZW1pdF9pbm5vX2RwLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IC0tLSAvZGV2L251bGwKPiAr KysgYi9kcml2ZXJzL2dwdS9kcm0vc3BhY2VtaXQvc3BhY2VtaXRfaW5ub19kcC5jClsgLi4uIF0K PiBAQCAtOTgyLDE5ICs5ODIsMTkgQEAgc3RhdGljIHZvaWQgc3BhY2VtaXRfZHBfaHdfc2V0X21z YV9hbmRfZW5hYmxlX3ZpZGVvKHN0cnVjdCBzcGFjZW1pdF9kcF9kZXYgKmRwLAo+ICAJCQkJCQkg ICAgY29uc3Qgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUsCj4gIAkJCQkJICAgICAgIGVu dW0gc3BhY2VtaXRfZHBfbGlua19yYXRlIHJhdGUsCj4gIAkJCQkJICAgICAgIGVudW0gc3BhY2Vt aXRfZHBfbGFuZV9jb3VudCBsYW5lcywKPiAgCQl1MzIgY29sb3JfZm9ybWF0KQo+ICB7Cj4gIAl1 NjQgaGJfbnVtOwo+ICAJdTMyIGxpbmtfcmF0ZTsKPiAgCXUzMiBmcDsgLyogUGl4ZWwgY2xvY2sg aW4gTUh6ICovCj4gIAl1MzIgYnBwLCBtaXNjMDsKPiAgCXUzMiB0dSwgdHVfZnJhYywgdHVfaW50 LCByZF90aHJlczsKPiAgCXUzMiBoc3luY19sZW47Cj4gIAo+ICAJLyogbW9kZS0+Y2xvY2sgdW5p dCBpcyBrSHosIGZwIHVuaXQgaXMgTUh6ICovCj4gIAlpZiAoZHAtPnVzZV9leHRfcGl4ZWxfY2xv Y2spCj4gIAkJZnAgPSBkcC0+cGl4ZWxfY2xvY2sgLyAxMDAwOwo+ICAJZWxzZQo+ICAJCWZwID0g bW9kZS0+Y2xvY2sgLyAxMDAwOwo+ICAKPiAgCWlmIChmcCA9PSAwKQo+ICAJCWZwID0gMTsgLyog UHJldmVudCBkaXZpc2lvbiBieSB6ZXJvICovCgpbU2V2ZXJpdHk6IEhpZ2hdCldpbGwgZGl2aWRp bmcgYnkgMTAwMCBoZXJlIHRydW5jYXRlIG5lY2Vzc2FyeSBwcmVjaXNpb24/CgpTaW5jZSBtb2Rl LT5jbG9jayAvIDEwMDAgZGlzY2FyZHMgdGhlIGZyYWN0aW9uYWwgcGFydCAoZm9yIGV4YW1wbGUs IGEgNzQuMjUKTUh6IGNsb2NrIGJlY29tZXMgNzQgTUh6KSwgdGhpcyB0cnVuY2F0ZWQgdmFsdWUg aXMgdXNlZCBpbiBjYWxjdWxhdGluZyB0aGUKVHJhbnNmZXIgVW5pdCBzaXplIGFuZCBob3Jpem9u dGFsIGJsYW5raW5nIGludGVydmFsLiBUaGlzIGRpc2NyZXBhbmN5IGNhbgpjYXVzZSB0aGUgZGlz cGxheSBjb250cm9sbGVyIGFuZCB0aGUgRFAgdHJhbnNtaXR0ZXIgdG8gZGlzYWdyZWUgb24gdGhl CnJlcXVpcmVkIGJhbmR3aWR0aCwgcmVzdWx0aW5nIGluIHRoZSBEUCBUWCBGSUZPIG92ZXJmbG93 aW5nIGFuZCBjb3JydXB0aW5nCnRoZSBkaXNwbGF5IGZvciBjb21tb24gc3RhbmRhcmQgcmVzb2x1 dGlvbnMgbGlrZSA3MjBwIGFuZCAxMDgwcC4KClsgLi4uIF0KPiBAQCAtMTI3OCw5ICsxMjc4LDkg QEAgc3RhdGljIGludCBzcGFjZW1pdF9kcF9hdXhfaTJjX3dyaXRlKHN0cnVjdCBzcGFjZW1pdF9k cF9kZXYgKmRwLCB1MzIgYWRkcmVzcywKPiAgCQkJCSAgICAgY29uc3QgdTggKmJ1Ziwgc2l6ZV90 IGxlbikKPiAgewo+ICAJc3RydWN0IGRybV9kcF9hdXhfbXNnIG1zZyA9IHsKPiAgCQkuYWRkcmVz cyA9IGFkZHJlc3MsCj4gIAkJLnJlcXVlc3QgPSBEUF9BVVhfSTJDX1dSSVRFLAoKW1NldmVyaXR5 OiBIaWdoXQpJcyBpdCBpbnRlbnRpb25hbCB0byBoYXJkY29kZSBEUF9BVVhfSTJDX1dSSVRFIGhl cmUgd2l0aG91dCBhbGxvd2luZyB0aGUKRFBfQVVYX0kyQ19NT1QgKE1pZGRsZSBPZiBUcmFuc2Fj dGlvbikgZmxhZyB0byBiZSBhcHBlbmRlZD8KClsgLi4uIF0KPiBAQCAtMTMyMCwxMSArMTMyMCwx MSBAQCBzdGF0aWMgaW50IHNwYWNlbWl0X2RwX2Nvbm5fZ2V0X2VkaWRfYmxvY2sodm9pZCAqZGF0 YSwgdTggKmJ1ZiwKPiAgCWludCByZXQsIHJldHJ5Owo+ICAJc2l6ZV90IG9mZnNldDsKPiAgCj4g IAlpZiAoc2VnbWVudCkgewo+ICAJCWZvciAocmV0cnkgPSAwOyByZXRyeSA8IDM7IHJldHJ5Kysp IHsKPiAgCQkJcmV0ID0gc3BhY2VtaXRfZHBfYXV4X2kyY193cml0ZShkcCwKPiAgCQkJCVNQQUNF TUlUX0RQX0REQ19TRUdNRU5UX0FERFIsICZzZWdtZW50LCAxKTsKPiAgCQkJaWYgKCFyZXQpCj4g IAkJCQlicmVhazsKPiAgCQl9CgpbU2V2ZXJpdHk6IEhpZ2hdCkNhbiB0aGlzIHNlZ21lbnQgd3Jp dGUgY2F1c2UgdGhlIGhhcmR3YXJlIHRvIGdlbmVyYXRlIGFuIEkyQyBTVE9QIGNvbmRpdGlvbj8K CkJlY2F1c2Ugc3BhY2VtaXRfZHBfYXV4X2kyY193cml0ZSgpIGxhY2tzIHRoZSBNT1QgZmxhZywg d3JpdGluZyB0aGUgRS1EREMKc2VnbWVudCBwb2ludGVyIHdpdGhvdXQgaXQgZGlyZWN0cyB0aGUg aGFyZHdhcmUgdG8gZ2VuZXJhdGUgYSBTVE9QIGNvbmRpdGlvbi4KQWNjb3JkaW5nIHRvIHRoZSBF LUREQyBzcGVjaWZpY2F0aW9uLCBhIFNUT1AgY29uZGl0aW9uIGltbWVkaWF0ZWx5IGFmdGVyCndy aXRpbmcgdGhlIHNlZ21lbnQgcG9pbnRlciBmb3JjZXMgdGhlIGRpc3BsYXkgRUVQUk9NIHRvIHJl c2V0IGl0cyBzZWdtZW50CnBvaW50ZXIgdG8gMC4KCkFzIGEgcmVzdWx0LCBzdWJzZXF1ZW50IHJl YWRzIG1pZ2h0IGFsd2F5cyBmZXRjaCBFRElEIGJsb2NrcyAwIGFuZCAxLCBtYWtpbmcKaXQgaW1w b3NzaWJsZSB0byBjb3JyZWN0bHkgcmVhZCBFRElEIGJsb2NrcyA+PSAyIChzdWNoIGFzIENUQS04 NjEgZXh0ZW5zaW9uCmJsb2NrcykgYW5kIHBvdGVudGlhbGx5IGJyZWFraW5nIHN1cHBvcnQgZm9y IGFkdmFuY2VkIHJlc29sdXRpb25zIGFuZCBhdWRpbwphbmQgSERSIGZlYXR1cmVzLgoKLS0gClNh c2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9wYXRjaHNldC8yMDI2MDcy NS1rMy1kaXNwbGF5LXYxLTAtNmRlMzRkODBlODZjQGdtYWlsLmNvbT9wYXJ0PTE1CgotLSAKbGlu dXgtcGh5IG1haWxpbmcgbGlzdApsaW51eC1waHlAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwczov L2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1waHkK