From: Stephen Hemminger <stephen@networkplumber.org>
To: Shreesh Adiga <16567adigashreesh@gmail.com>
Cc: Wathsala Vithanage <wathsala.vithanage@arm.com>, dev@dpdk.org
Subject: Re: [PATCH] net/crc: add 4x folding loop for aarch64 NEON implementation
Date: Sun, 26 Jul 2026 09:41:21 -0700 [thread overview]
Message-ID: <20260726094121.51db3928@phoenix.local> (raw)
In-Reply-To: <20260706092537.1252921-1-16567adigashreesh@gmail.com>
On Mon, 6 Jul 2026 14:54:14 +0530
Shreesh Adiga <16567adigashreesh@gmail.com> wrote:
> Add a 64-byte loop that maintains 4 fold registers and processes
> 64 bytes at a time. The 4x fold registers is then reduced to 16 byte
> single fold, similar to x86 SSE implementation. This technique is
> described in the paper by Intel:
> "Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction"
>
> This results in roughly 2x performance improvement due to better ILP
> for large input sizes like 1024 observed on Cortex-X925.
>
> Also removed the special handling of len 16 to 31 similar to x86 SSE
> implementation.
>
> Signed-off-by: Shreesh Adiga <16567adigashreesh@gmail.com>
> ---
Applied to next-net
prev parent reply other threads:[~2026-07-26 17:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-16 9:11 [PATCH] net/crc: add 4x folding loop for aarch64 NEON implementation Shreesh Adiga
2026-07-03 14:31 ` Stephen Hemminger
2026-07-06 9:24 ` Shreesh Adiga
2026-07-26 16:41 ` Stephen Hemminger [this message]
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