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Sun, 26 Jul 2026 07:51:38 -0700 (PDT) Received: from localhost.localdomain ([82.40.42.115]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cfde81d7f5sm20934195ad.83.2026.07.26.07.51.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 26 Jul 2026 07:51:36 -0700 (PDT) From: Jack Wang <163wangjack@gmail.com> To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Peter Maydell , Alistair Francis , Fabiano Rosas , Laurent Vivier , qemu-arm@nongnu.org, qemu-rust@nongnu.org, caojunze424@gmail.com, Jack Wang <163wangjack@gmail.com> Subject: [RFC PATCH v1 0/5] hw/gpio: STM32F1xx GPIO controller in Rust Date: Sun, 26 Jul 2026 22:51:14 +0800 Message-ID: <20260726145119.19881-1-163wangjack@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=163wangjack@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_STARTS_WITH_NUMS=0.738, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi all, This RFC adds an STM32F1xx GPIO controller modelled in Rust, following the existing rust/hw/char/pl011 device as a template. The register logic (CRL/CRH mode+config decode and the IDR update algorithm) is a direct port of the C model in hw/gpio/stm32l4x5_gpio.c; the STM32F1xx GPIO block (RM0008) is the same IP used by the upstream stm32f100_soc. This series is currently stacked on an out-of-tree STM32F103 SoC and board that are not yet upstream which is https://github.com/shandianchengzi/qemu But the commit(the initialize logic and gpio architecture) is both capable for stm32f100.This is the reason that struct name is stm32f1xx. Patch 3 ("hw/arm/stm32f103: instantiate and mapGPIO ports") therefore touches files that do not exist in mainline and willnot apply cleanly on its own. I am sending this as an RFC to get feedback onthe Rust device model and its integration now, before the SoC lands, rather than as an apply-ready series . Once the SoC is upstream (or if you I can retarget the device at the existing stm32f100_soc), I will resend a non-RFC series. checkpatch reports SPDX warnings on Kconfig/trace-events/Cargo.toml/ meson.build and "MAINTAINERS need updating" on the new files. These are false positives: matching rust/hw/char/pl011, these file types carry no SPDX header in-tree, and MAINTAINERS already gains an entry covering rust/hw/gpio/ and the qtest in this series. Anyway this is my first time to generate rust model build so sorry for some mistakes. And any help or tip are welcomed Jack Wang (5): hw/gpio: add stm32f1xx GPIO device model (Rust) rust: add hw/gpio crate to the workspace hw/arm/stm32f103: instantiate and map GPIO ports tests/qtest: add stm32f103 GPIO test rust/hw/gpio: add native unit tests MAINTAINERS | 7 + hw/arm/Kconfig | 1 + hw/arm/stm32f103_board.c | 2 +- hw/arm/stm32f103_soc.c | 54 ++- hw/gpio/Kconfig | 5 + hw/gpio/trace-events | 7 + include/hw/arm/stm32f103_soc.h | 9 + rust/Cargo.lock | 17 +- rust/Cargo.toml | 18 + rust/hw/Kconfig | 1 + rust/hw/gpio/Cargo.toml | 28 ++ rust/hw/gpio/Kconfig | 2 + rust/hw/gpio/meson.build | 54 +++ rust/hw/gpio/src/bindings.rs | 19 ++ rust/hw/gpio/src/gpio.rs | 539 ++++++++++++++++++++++++++++++ rust/hw/gpio/src/lib.rs | 3 + rust/hw/gpio/tests/tests.rs | 191 +++++++++++ rust/hw/meson.build | 1 + tests/qtest/meson.build | 4 + tests/qtest/stm32f103_gpio-test.c | 328 ++++++++++++++++++ 20 files changed, 1281 insertions(+), 9 deletions(-) create mode 100644 rust/hw/gpio/Cargo.toml create mode 100644 rust/hw/gpio/Kconfig create mode 100644 rust/hw/gpio/meson.build create mode 100644 rust/hw/gpio/src/bindings.rs create mode 100644 rust/hw/gpio/src/gpio.rs create mode 100644 rust/hw/gpio/src/lib.rs create mode 100644 rust/hw/gpio/tests/tests.rs create mode 100644 tests/qtest/stm32f103_gpio-test.c -- 2.53.0