Re: [PATCH 1/2] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The patch adds `compatible = "pciclass,0604"` to `pcieport0` but fails to add the same required property to `pcieport1`.
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--- Patch [1]: [PATCH 1/2] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port ---
commit 0ca797402b7e421fe911e89c620b4ebd792ff4af
Author: Wei Deng <wei.deng@oss.qualcomm.com>

arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

This commit adds the "pciclass,0604" compatible string to the pcieport0
node in monaco.dtsi. This enables the PCI subsystem to associate the
device tree node with the PCI-to-PCI bridge device, allowing downstream
endpoints to be correctly matched.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 64fc0d592282c..438ccf6eba64d 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2393,6 +2393,7 @@ opp-32000000 {
>  			};
>  
>  			pcieport0: pcie@0 {
> +				compatible = "pciclass,0604";
>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;

[Severity: High]
This is a pre-existing issue, but should the same compatible property be
added to the pcieport1 node in this file?

Looking further down in arch/arm64/boot/dts/qcom/monaco.dtsi, the pcieport1
node is missing this property:

			pcieport1: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;
				...

Without the compatible property, the device tree node for pcieport1 will not
spawn a platform device, which prevents power control drivers like
pci-pwrctrl-slot from binding. 

Will this cause downstream nodes (such as M.2 endpoints) connected to the
second PCIe controller (pcie1) to fail to match or correctly power on?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727-b4-monaco-evk-m2-v1-v1-0-5429cce68599@oss.qualcomm.com?part=1