Re: [PATCH v2 5/6] arm64: dts: qcom: kodiak: mark PCIe root port as bridge

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The patch adds `compatible = "pciclass,0604"` to the `pcie0_port` root port node in `kodiak.dtsi` to ensure the PCI core and slot power control drivers can associate the DT node with the enumerated PCI-to-PCI bridge, which enables child node matching. However, the patch fails to apply this exact same fix to the sibling `pcie1_port0` root port node.
--

--- Patch [5]: [PATCH v2 5/6] arm64: dts: qcom: kodiak: mark PCIe root port as bridge ---
commit 570e5e44fe4845eb64dbbfbc0bb38b9d4ae991da
Author: Rahul Samana <rahul.samana@oss.qualcomm.com>

arm64: dts: qcom: kodiak: mark PCIe root port as bridge

The patch adds the compatible = "pciclass,0604" property to the pcie0_port
device tree node. This allows the PCI core to associate the OF node with
the enumerated PCI-to-PCI bridge device, enabling proper matching for child
nodes.

> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> index fa540d8c2615d..12594967d2c26 100644
> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> @@ -2296,6 +2296,7 @@ pcie0: pcie@1c00000 {
>  			status = "disabled";
>  
>  			pcie0_port: pcie@0 {
> +				compatible = "pciclass,0604";
>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;

[Severity: High]
This isn't a bug introduced by this patch, but should the exact same fix be
applied to the secondary PCIe root port node (pcie1_port0)?

Looking further down in arch/arm64/boot/dts/qcom/kodiak.dtsi, pcie1_port0
has an identical structure but is missing the "pciclass,0604" property:

			pcie1_port0: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

Without this property on pcie1_port0, won't devices connected to the
secondary PCIe port fail to properly associate their OF nodes with the
enumerated PCI devices?

This could prevent downstream devices from acquiring essential DT properties
like regulators and GPIOs.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727-rb3-industrial-bt-uart-v2-0-2d100f30e202@oss.qualcomm.com?part=5