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Wed, 29 Jul 2026 08:16:44 +0000 (GMT) Received: from osiris (unknown [9.111.35.133]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTPS; Wed, 29 Jul 2026 08:16:43 +0000 (GMT) Date: Wed, 29 Jul 2026 10:16:42 +0200 From: Heiko Carstens To: Mark Rutland Subject: Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Message-ID: <20260729081642.17504Be5-hca@linux.ibm.com> References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-7-mark.rutland@arm.com> <20260728165129.114152B00-hca@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260728165129.114152B00-hca@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI5MDA2MiBTYWx0ZWRfX4gsAghXJd81u EKoL71/7s36p6QbvPgxG5hV/xn84bYHdycNALAKCqN88BedTi+o8t6MyVo3UfcERClDWPFp6/fL 4jVuxCGgcy9lsCmOwH/9rcdi1Pv0Kso= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI5MDA2MiBTYWx0ZWRfX16Xep3mm6jYQ mZaB4URsZGHX28GEdU2xNcfZJcKKQANIToTRCv5OqLeklomntmwZi00UPplK/bc7uFAvKwhvhDS RLY2IgbvCJnD9liWryqHJQBMfXkerR/HmSUJizky272djA7qhOAjUOD8MmSTFfsYyJm1c5szOik gpHDsicekp2Ub9r0cysNYAx4mLS/PWdx+MChTOkPWvC1hF3BOWnebmFPUuYfQ4vDrDtw9HHcctg 5YiPBFXhj6yiFS2nLZnml7CRq65GFow3jjEkYCU+ZPZTvxUKBEZJqADRMu8ByMBOsMZrykPDfMJ 0J5g7gIkR3e1G7AeuWihii8aAFnpSLdTjFCuoIfgGJNPPSnvZTwDwTrjz3Oi+OHZPqaUeQ86GlM KGqKykAkKMItv3g0BEyOo4Xc5mJVDsz0Ie+f/VVEz7YJzDFMPPznvC9bgevezJGp0tzQSTuFwew D/u3Icbln7+MB+HASzg== X-Authority-Analysis: v=2.4 cv=b5WCJNGx c=1 sm=1 tr=0 ts=6a69b6ef cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=uay6Ie4fmS4UotqiDDIA:9 a=CjuIK1q_8ugA:10 X-Proofpoint-GUID: sUXiipTfwPqxwsTsmhZFP6rswM8B8C_N X-Proofpoint-ORIG-GUID: sUXiipTfwPqxwsTsmhZFP6rswM8B8C_N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-29_03,2026-07-28_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607290062 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260729_011701_299709_BBCC12B0 X-CRM114-Status: GOOD ( 19.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vladimir.murzin@arm.com, peterz@infradead.org, maz@kernel.org, ruanjinjie@huawei.com, linux-kernel@vger.kernel.org, yang@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, ardb@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 28, 2026 at 06:51:29PM +0200, Heiko Carstens wrote: > > If an exception is taken from within the critical section, the exception > > return code will adjust to be the current CPU's offset, and will > > adjust to be ( + ). Distinct registers are used for > > , , and , so that the fixup can be applied safely at any > > point during the critical section. > > This looks indeed better than that what I came up with for s390. > > It works without comparing instruction pointers, also works out-of-the-box > with kprobes, and hence the fixup is much simpler. I guess I'll try to change > s390 to a similar mechanism and see what the result will look like. It will > use one more instruction to the current version, as far as I can tell now, but > the simplicity is probably worth it. Hm.. unfortunately the required instructions (like an add that adds two registers and puts the result in a third register), are not available on all supported architecture levels on s390. But there are also other short comings with the available instructions - so I don't think your approach will fly on s390. Too bad. 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Wed, 29 Jul 2026 08:16:44 +0000 (GMT) Received: from osiris (unknown [9.111.35.133]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTPS; Wed, 29 Jul 2026 08:16:43 +0000 (GMT) Date: Wed, 29 Jul 2026 10:16:42 +0200 From: Heiko Carstens To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, maz@kernel.org, peterz@infradead.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Message-ID: <20260729081642.17504Be5-hca@linux.ibm.com> References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-7-mark.rutland@arm.com> <20260728165129.114152B00-hca@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260728165129.114152B00-hca@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI5MDA2MiBTYWx0ZWRfX4gsAghXJd81u EKoL71/7s36p6QbvPgxG5hV/xn84bYHdycNALAKCqN88BedTi+o8t6MyVo3UfcERClDWPFp6/fL 4jVuxCGgcy9lsCmOwH/9rcdi1Pv0Kso= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI5MDA2MiBTYWx0ZWRfX16Xep3mm6jYQ mZaB4URsZGHX28GEdU2xNcfZJcKKQANIToTRCv5OqLeklomntmwZi00UPplK/bc7uFAvKwhvhDS RLY2IgbvCJnD9liWryqHJQBMfXkerR/HmSUJizky272djA7qhOAjUOD8MmSTFfsYyJm1c5szOik gpHDsicekp2Ub9r0cysNYAx4mLS/PWdx+MChTOkPWvC1hF3BOWnebmFPUuYfQ4vDrDtw9HHcctg 5YiPBFXhj6yiFS2nLZnml7CRq65GFow3jjEkYCU+ZPZTvxUKBEZJqADRMu8ByMBOsMZrykPDfMJ 0J5g7gIkR3e1G7AeuWihii8aAFnpSLdTjFCuoIfgGJNPPSnvZTwDwTrjz3Oi+OHZPqaUeQ86GlM KGqKykAkKMItv3g0BEyOo4Xc5mJVDsz0Ie+f/VVEz7YJzDFMPPznvC9bgevezJGp0tzQSTuFwew D/u3Icbln7+MB+HASzg== X-Authority-Analysis: v=2.4 cv=b5WCJNGx c=1 sm=1 tr=0 ts=6a69b6ef cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=uay6Ie4fmS4UotqiDDIA:9 a=CjuIK1q_8ugA:10 X-Proofpoint-GUID: sUXiipTfwPqxwsTsmhZFP6rswM8B8C_N X-Proofpoint-ORIG-GUID: sUXiipTfwPqxwsTsmhZFP6rswM8B8C_N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-29_03,2026-07-28_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607290062 On Tue, Jul 28, 2026 at 06:51:29PM +0200, Heiko Carstens wrote: > > If an exception is taken from within the critical section, the exception > > return code will adjust to be the current CPU's offset, and will > > adjust to be ( + ). Distinct registers are used for > > , , and , so that the fixup can be applied safely at any > > point during the critical section. > > This looks indeed better than that what I came up with for s390. > > It works without comparing instruction pointers, also works out-of-the-box > with kprobes, and hence the fixup is much simpler. I guess I'll try to change > s390 to a similar mechanism and see what the result will look like. It will > use one more instruction to the current version, as far as I can tell now, but > the simplicity is probably worth it. Hm.. unfortunately the required instructions (like an add that adds two registers and puts the result in a third register), are not available on all supported architecture levels on s390. But there are also other short comings with the available instructions - so I don't think your approach will fly on s390. Too bad.