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Wed, 29 Jul 2026 05:07:48 -0700 (PDT) Received: from q-System-Product-Name ([129.227.183.200]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84ea0055133sm1309570b3a.18.2026.07.29.05.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2026 05:07:48 -0700 (PDT) From: "Bingyu.Xian" To: Anup Patel Cc: Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Quan Zhou , stable@vger.kernel.org, Bingyu Xian Subject: [PATCH v3 3/3] RISC-V: KVM: Widen G-stage fault address to gpa_t Date: Wed, 29 Jul 2026 20:07:33 +0800 Message-ID: <20260729120733.829457-4-shanbeeyoo@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260729120733.829457-1-shanbeeyoo@gmail.com> References: <20260729075230.743030-1-shanbeeyoo@gmail.com> <20260729120733.829457-1-shanbeeyoo@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260729_050749_180837_898331AC X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org fault_addr in gstage_page_fault() and the fault_addr parameter of kvm_riscv_vcpu_mmio_load/store() are unsigned long. On RV32 with Sv32x4, guest physical addresses are 34 bits, so a 32-bit unsigned long truncates bits 32/33 at two points: - reconstruction: fault_addr = (trap->htval << 2) | ... is evaluated in 32-bit arithmetic, dropping bits 32/33 before widening; - the MMIO handler call: even with the local widened, the handler's unsigned long parameter narrows it back to 32 bits, aliasing accesses above 4 GB into the low 4 GB. Widen fault_addr to gpa_t end to end: the local in gstage_page_fault(), the (gpa_t) cast before the <<2 shift, and the fault_addr parameters of kvm_riscv_vcpu_mmio_load/store(). The handlers' internal uses (run->mmio.phys_addr is __u64, kvm_io_bus_read/write() take gpa_t) are already 64-bit, so no further changes are needed. Also in preparation for sharing a common struct kvm_page_fault across architectures, where fault_addr is gpa_t. No functional change on RV64. Fixes: 9d05c1fee837 ("RISC-V: KVM: Implement stage2 page table programming") Assisted-by: YuanSheng: deepseek-v4-pro Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Bingyu Xian --- arch/riscv/include/asm/kvm_vcpu_insn.h | 4 ++-- arch/riscv/kvm/vcpu_exit.c | 5 +++-- arch/riscv/kvm/vcpu_insn.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_insn.h b/arch/riscv/include/asm/kvm_vcpu_insn.h index 350011c83581..a5c50dd4a884 100644 --- a/arch/riscv/include/asm/kvm_vcpu_insn.h +++ b/arch/riscv/include/asm/kvm_vcpu_insn.h @@ -38,10 +38,10 @@ int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, struct kvm_cpu_trap *trap); int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst); int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst); int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 6c8530b9f29e..28cf9b27bb07 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -17,12 +17,13 @@ static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, { struct kvm_gstage_mapping host_map; struct kvm_memory_slot *memslot; - unsigned long hva, fault_addr; + unsigned long hva; + gpa_t fault_addr; bool writable; gfn_t gfn; int ret; - fault_addr = (trap->htval << 2) | (trap->stval & 0x3); + fault_addr = ((gpa_t)trap->htval << 2) | (trap->stval & 0x3); gfn = fault_addr >> PAGE_SHIFT; memslot = gfn_to_memslot(vcpu->kvm, gfn); hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable); diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index f09f9251d1f0..6506411a3f78 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -371,7 +371,7 @@ int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, * Returns < 0 to report failure and exit run-loop */ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst) { u8 data_buf[8]; @@ -494,7 +494,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, * Returns < 0 to report failure and exit run-loop */ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst) { u8 data8; -- 2.54.0 -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAFE3C54FCD for ; Wed, 29 Jul 2026 12:08:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 29 Jul 2026 05:07:48 -0700 (PDT) From: "Bingyu.Xian" To: Anup Patel Cc: Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Quan Zhou , stable@vger.kernel.org, Bingyu Xian Subject: [PATCH v3 3/3] RISC-V: KVM: Widen G-stage fault address to gpa_t Date: Wed, 29 Jul 2026 20:07:33 +0800 Message-ID: <20260729120733.829457-4-shanbeeyoo@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260729120733.829457-1-shanbeeyoo@gmail.com> References: <20260729075230.743030-1-shanbeeyoo@gmail.com> <20260729120733.829457-1-shanbeeyoo@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260729_050749_190361_C4D1A077 X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org fault_addr in gstage_page_fault() and the fault_addr parameter of kvm_riscv_vcpu_mmio_load/store() are unsigned long. On RV32 with Sv32x4, guest physical addresses are 34 bits, so a 32-bit unsigned long truncates bits 32/33 at two points: - reconstruction: fault_addr = (trap->htval << 2) | ... is evaluated in 32-bit arithmetic, dropping bits 32/33 before widening; - the MMIO handler call: even with the local widened, the handler's unsigned long parameter narrows it back to 32 bits, aliasing accesses above 4 GB into the low 4 GB. Widen fault_addr to gpa_t end to end: the local in gstage_page_fault(), the (gpa_t) cast before the <<2 shift, and the fault_addr parameters of kvm_riscv_vcpu_mmio_load/store(). The handlers' internal uses (run->mmio.phys_addr is __u64, kvm_io_bus_read/write() take gpa_t) are already 64-bit, so no further changes are needed. Also in preparation for sharing a common struct kvm_page_fault across architectures, where fault_addr is gpa_t. No functional change on RV64. Fixes: 9d05c1fee837 ("RISC-V: KVM: Implement stage2 page table programming") Assisted-by: YuanSheng: deepseek-v4-pro Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Bingyu Xian --- arch/riscv/include/asm/kvm_vcpu_insn.h | 4 ++-- arch/riscv/kvm/vcpu_exit.c | 5 +++-- arch/riscv/kvm/vcpu_insn.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_insn.h b/arch/riscv/include/asm/kvm_vcpu_insn.h index 350011c83581..a5c50dd4a884 100644 --- a/arch/riscv/include/asm/kvm_vcpu_insn.h +++ b/arch/riscv/include/asm/kvm_vcpu_insn.h @@ -38,10 +38,10 @@ int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, struct kvm_cpu_trap *trap); int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst); int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst); int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 6c8530b9f29e..28cf9b27bb07 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -17,12 +17,13 @@ static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, { struct kvm_gstage_mapping host_map; struct kvm_memory_slot *memslot; - unsigned long hva, fault_addr; + unsigned long hva; + gpa_t fault_addr; bool writable; gfn_t gfn; int ret; - fault_addr = (trap->htval << 2) | (trap->stval & 0x3); + fault_addr = ((gpa_t)trap->htval << 2) | (trap->stval & 0x3); gfn = fault_addr >> PAGE_SHIFT; memslot = gfn_to_memslot(vcpu->kvm, gfn); hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable); diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index f09f9251d1f0..6506411a3f78 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -371,7 +371,7 @@ int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, * Returns < 0 to report failure and exit run-loop */ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst) { u8 data_buf[8]; @@ -494,7 +494,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, * Returns < 0 to report failure and exit run-loop */ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst) { u8 data8; -- 2.54.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pz2-f0.google.com (mail-pz2-f0.google.com [74.125.228.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420B247D933 for ; Wed, 29 Jul 2026 12:07:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.228.0 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785326870; cv=none; b=QFuE7xxDQXw6YJEJuhg3JjUKFOc8AvHJiE2/SDGt4lATmc7waioEGyXlIykY0p8ExLX3cjSu+NFjmZiN5ligy9rnve1ldtmElFrlporY+BXB2OpLrybg92LkGCYtS+FmhQuDo12NGC24oZ42V7vjxaa6pX7ZSWijGOZXSLiIdX8= ARC-Message-Signature:i=1; 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Wed, 29 Jul 2026 05:07:48 -0700 (PDT) Received: from q-System-Product-Name ([129.227.183.200]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84ea0055133sm1309570b3a.18.2026.07.29.05.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2026 05:07:48 -0700 (PDT) From: "Bingyu.Xian" To: Anup Patel Cc: Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Quan Zhou , stable@vger.kernel.org, Bingyu Xian Subject: [PATCH v3 3/3] RISC-V: KVM: Widen G-stage fault address to gpa_t Date: Wed, 29 Jul 2026 20:07:33 +0800 Message-ID: <20260729120733.829457-4-shanbeeyoo@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260729120733.829457-1-shanbeeyoo@gmail.com> References: <20260729075230.743030-1-shanbeeyoo@gmail.com> <20260729120733.829457-1-shanbeeyoo@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit fault_addr in gstage_page_fault() and the fault_addr parameter of kvm_riscv_vcpu_mmio_load/store() are unsigned long. On RV32 with Sv32x4, guest physical addresses are 34 bits, so a 32-bit unsigned long truncates bits 32/33 at two points: - reconstruction: fault_addr = (trap->htval << 2) | ... is evaluated in 32-bit arithmetic, dropping bits 32/33 before widening; - the MMIO handler call: even with the local widened, the handler's unsigned long parameter narrows it back to 32 bits, aliasing accesses above 4 GB into the low 4 GB. Widen fault_addr to gpa_t end to end: the local in gstage_page_fault(), the (gpa_t) cast before the <<2 shift, and the fault_addr parameters of kvm_riscv_vcpu_mmio_load/store(). The handlers' internal uses (run->mmio.phys_addr is __u64, kvm_io_bus_read/write() take gpa_t) are already 64-bit, so no further changes are needed. Also in preparation for sharing a common struct kvm_page_fault across architectures, where fault_addr is gpa_t. No functional change on RV64. Fixes: 9d05c1fee837 ("RISC-V: KVM: Implement stage2 page table programming") Assisted-by: YuanSheng: deepseek-v4-pro Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Bingyu Xian --- arch/riscv/include/asm/kvm_vcpu_insn.h | 4 ++-- arch/riscv/kvm/vcpu_exit.c | 5 +++-- arch/riscv/kvm/vcpu_insn.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_insn.h b/arch/riscv/include/asm/kvm_vcpu_insn.h index 350011c83581..a5c50dd4a884 100644 --- a/arch/riscv/include/asm/kvm_vcpu_insn.h +++ b/arch/riscv/include/asm/kvm_vcpu_insn.h @@ -38,10 +38,10 @@ int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, struct kvm_cpu_trap *trap); int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst); int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst); int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 6c8530b9f29e..28cf9b27bb07 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -17,12 +17,13 @@ static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, { struct kvm_gstage_mapping host_map; struct kvm_memory_slot *memslot; - unsigned long hva, fault_addr; + unsigned long hva; + gpa_t fault_addr; bool writable; gfn_t gfn; int ret; - fault_addr = (trap->htval << 2) | (trap->stval & 0x3); + fault_addr = ((gpa_t)trap->htval << 2) | (trap->stval & 0x3); gfn = fault_addr >> PAGE_SHIFT; memslot = gfn_to_memslot(vcpu->kvm, gfn); hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable); diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index f09f9251d1f0..6506411a3f78 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -371,7 +371,7 @@ int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, * Returns < 0 to report failure and exit run-loop */ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst) { u8 data_buf[8]; @@ -494,7 +494,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, * Returns < 0 to report failure and exit run-loop */ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long fault_addr, + gpa_t fault_addr, unsigned long htinst) { u8 data8; -- 2.54.0