From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DD8D331EA5 for ; Thu, 30 Jul 2026 00:45:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785372303; cv=none; b=mTCyW9FbVgcTfeOlZbv/o+InAYqv/mNds9ScTI0pihmw3LQkpKFdsEdqfqvANpfOa9xg5xutVg6tpmltL6yyQ3KpYKDMJjQrgfuvbrLYwSLD9u1tJnWAnGCZqV5uhRR6woym3WIOTqCmHBMhxUPWKJLmtHeY0mRSxAnNuTIoa9o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785372303; c=relaxed/simple; bh=n6gKmerUoBm57loaU3BDfyoIadkMdhbaaTwAFNKv79k=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type; b=ecsZdW1lPbjR0btadrVuumAWfLeKZx5+L6j1A19raQ4385ZqQ4iB/axkSGE9he33Tl9HAvJKcifjd3pxKVecQaLBIlNy08pvoRPDUXUOPhp9KyhGUKC6s/MNao6V4jkKgbNcJODqvs2vrmUrRSAcaRP42xjdqgWebRIxipFcQU4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=surriel.com; dkim=pass (2048-bit key) header.d=surriel.com header.i=@surriel.com header.b=Uqr/elqD; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=surriel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=surriel.com header.i=@surriel.com header.b="Uqr/elqD" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=surriel.com ; s=mail; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=KbFKUSDJPP8K8eTIvMJmgzzX5vohGHpxY6FLdXqBvao=; b=Uqr/elqD5+KB8XrBPKA39ls7Tp p2YFNy2yFU1FNhbn5Pv/iXRJdcBypOPSk1mDXWqRv+EpXVuSsaTjvJApx8Mu1hAtyiNXx3kTrXAUi mRDUAWBH45rBZUxSe6NGg48QaM0wSpITgRf8PTwv+dBgGVqSNBWlL+yaYTgpdOfeolA6gGf2k6dMr A1TXlzB14nEn6RXJj6nHGQIC9T/gG3kkqB28q94oFsWP0u2Yf8eigxz1vL0B3v8gZqbgrsLD59iKB MTBUe7ui/rtyWRDPHQtPYBJxuviG59iivHKlBtxlhXE3WpL360RrxBJ5a85wcVkgFx2hJg6uJx1J2 t3Eqh/Gw==; Received: from [2601:18c:8180:83cc:5a47:caff:fe78:8708] (helo=fangorn) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1wpEsE-00000000251-0p7P; Wed, 29 Jul 2026 20:43:46 -0400 Date: Wed, 29 Jul 2026 20:43:41 -0400 From: Rik van Riel To: Borislav Petkov Cc: Dave Hansen , Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com Subject: [PATCH] add tlbi=off to disable INVLPGB Message-ID: <20260729204341.3eb0b5ea@fangorn> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.49; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit With the recently found INVLPGB / TLBSYNC issue, there has been some interest in disabling invlpgb TLB flushing, in order to rule out that CPU issue as a cause of userspace crashes. The top search result shows "clearcpuid=invlpgb" However, invlpgb is not actually in x86_cap_flags, so booting with clearcpuid=invlpgb results in an error message: clearcpuid: unknown CPU flag: invlpgb Add a kernel commandline option to turn off AMD TLBI, to make it easier to rule out INVLPGB as a cause of userspace crashes. Verified by booting a Bergamo system with tlbi=off and checking that the INVLPGB bit is clear in boot_cpu_data.x86_capability Signed-off-by: Rik van Riel Suggested-by: Borislav Petkov --- arch/x86/mm/init_64.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index d57f29ca23a5..412ad9cd5fe2 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -130,6 +130,19 @@ static int __init nonx32_setup(char *str) } __setup("noexec32=", nonx32_setup); +/* + * tlbi=off + * + * Control AMD TLBI feature (INVLPGB TLB flushing) + */ +static int __init tlbi_setup(char *str) +{ + if (!strcmp(str, "off")) + setup_clear_cpu_cap(X86_FEATURE_INVLPGB); + return 1; +} +__setup("tlbi=", tlbi_setup); + static void sync_global_pgds_l5(unsigned long start, unsigned long end) { unsigned long addr; -- 2.53.0-Meta