Re: [PATCH v2] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing Context Synchronization Event (CSE) after writing to `SCTLR_EL1`.
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--- Patch [1]: [PATCH v2] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue ---
commit 174c9667365c79e4a6011c183eeb84b1ff94a880
Author: Peng Fan <peng.fan@nxp.com>

arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

This commit adds a workaround for the NXP i.MX8QuadMax SoC cache coherency
issue (ERR050104). It upgrades targeted TLBI and IC IVAU operations to
broadcast-all variants via static keys and alternatives, and disables KVM
support for the affected hardware.

Link: https://lore.kernel.org/all/20230420112952.28340-1-iivanov@suse.de/

> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 5db8f0619e4bc..1866eeec27cab 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c

[ ... ]

> @@ -200,6 +201,16 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
>  	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);

[Severity: High]
This is a pre-existing issue, but does this write to SCTLR_EL1 require an
immediate isb() barrier before returning?

Writing to a control-plane system register like SCTLR_EL1 in
cpu_enable_cache_maint_trap() without an immediate Context Synchronization
Event (CSE) violates architectural invariants. Returning without an isb()
leaves the CPU pipeline in an undefined state, which could lead to spurious
exceptions or boot-time hangs on affected platforms.

>  }

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260730-imx8qm-cache-coherency-v2-1-5651aeb1af16@nxp.com?part=1