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Thu, 30 Jul 2026 11:04:07 -0700 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 1/1] rust: pci: add extended capability and SR-IOV support Date: Thu, 30 Jul 2026 21:03:47 +0300 Message-ID: <20260730180349.771719-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260730180349.771719-1-zhiw@nvidia.com> References: <20260730180349.771719-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|SJ0PR12MB6880:EE_ X-MS-Office365-Filtering-Correlation-Id: 324542bb-eca3-4972-6f6d-08deee650226 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|36860700016|1800799024|82310400026|6133799003|10067099003|11063799006|56012099006|22082099003|18002099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YrI+rACdWUyaIZCRQoQ+CAQv8gCwvaqMZCO+lYrnStr+Qt5cOTC0A3bRVZesaz0e/flM/xAgtLIBKPHa3ynwGkB/s7iwx25PvBAuJ1LRMpg4vXxfC0vzBlIOLmDiYga66EIdwqRawWFGoYv7D8OuRVVvWEIII7jpZTnqOEjugJe0YWW5nAburlJs4gGw8NpnEzkYTS+6/KYGVbnY9r4WyV1LwZawV4uGir7zHablyoHaKwAvUKUbJkyWTwdIFMjjZVItwyW1MmkUCPRjG246e/ZqrvMgQ+k+Kb3jCQr1Pw8hkl+eiLAxvZidHzL+Bhs2Fhy/K8qGw7YcX/3nkXxZ3jjDULabn++vfWnPTJMhRuEt90jPstZg+u5jGlwOujBLPoxuD9iVFsPzOpNFbkjw/JQN0YHls0s2sn6G4Ep2GOoXfJC4FcCwCcpqSsp0+drY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2026 18:04:32.7156 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 324542bb-eca3-4972-6f6d-08deee650226 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6880 The SR-IOV extended capability describes VF topology and VF BARs. Expose this information through the Rust PCI abstraction so drivers can use the existing typed configuration-space accessors instead of raw bindings. Define ExtCapability to associate a capability ID with a register layout, and add ConfigSpace::find_ext_capability() to locate and project that layout. Bound the view at the next capability or the end of extended configuration space. Add ExtSriovRegs and a decoded VF BAR helper that returns the address, width, and next configuration-space slot, using PCI_SRIOV_NUM_BARS for the number of BAR slots. Since PCI_EXT_CAP_NEXT() is a function-like macro, expose it through a Rust helper. Link: https://lore.kernel.org/rust-for-linux/20260714165827.2937960-1-zhiw@nvidia.com/ Cc: Alexandre Courbot Cc: Gary Guo Signed-off-by: Zhi Wang --- rust/helpers/pci.c | 5 + rust/kernel/pci.rs | 8 ++ rust/kernel/pci/cap.rs | 251 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 rust/kernel/pci/cap.rs diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c index 4ebf256dff23..b946b14d79e4 100644 --- a/rust/helpers/pci.c +++ b/rust/helpers/pci.c @@ -24,6 +24,11 @@ __rust_helper bool rust_helper_dev_is_pci(const struct device *dev) return dev_is_pci(dev); } +__rust_helper u32 rust_helper_pci_ext_cap_next(u32 header) +{ + return PCI_EXT_CAP_NEXT(header); +} + #ifndef CONFIG_PCI_IOV __rust_helper unsigned int rust_helper_pci_sriov_get_totalvfs(struct pci_dev *pdev) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 9f19ccd5905c..008c2770a3f3 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -32,10 +32,18 @@ }, }; +mod cap; mod id; mod io; mod irq; +pub use self::cap::{ + ExtCapId, + ExtCapability, + ExtSriovCapability, + ExtSriovRegs, + ExtSriovVfBar, // +}; pub use self::id::{ Class, ClassMask, diff --git a/rust/kernel/pci/cap.rs b/rust/kernel/pci/cap.rs new file mode 100644 index 000000000000..004ee62bd089 --- /dev/null +++ b/rust/kernel/pci/cap.rs @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! PCI extended capability support. + +use super::{ + io::ConfigSpaceBackend, + ConfigSpace, + Extended, // +}; +use crate::{ + bindings, + io::{ + Io, + IoBackend, + Region, // + }, + prelude::*, + ptr::KnownSize, // +}; + +/// Number of VF BAR register slots in an SR-IOV capability. +// CAST: `PCI_SRIOV_NUM_BARS` is 6, which fits in `usize`. +const NUM_VF_BARS: usize = bindings::PCI_SRIOV_NUM_BARS as usize; + +/// Attribute bits encoded in the low DWORD of a memory BAR. +const VF_MEMORY_BAR_ATTRIBUTE_BITS: u32 = bindings::PCI_BASE_ADDRESS_SPACE + | bindings::PCI_BASE_ADDRESS_MEM_TYPE_MASK + | bindings::PCI_BASE_ADDRESS_MEM_PREFETCH; + +/// PCI extended capability IDs. +#[repr(u16)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum ExtCapId { + /// Single Root I/O Virtualization. + // CAST: `PCI_EXT_CAP_ID_SRIOV` is `0x10`, which fits in `u16`. + Sriov = bindings::PCI_EXT_CAP_ID_SRIOV as u16, +} + +impl ExtCapId { + fn as_raw(self) -> u16 { + self as u16 + } +} + +/// A typed PCI extended capability register layout. +/// +/// Implementors describe the register layout of one extended capability. The layout must start at +/// the extended capability header, and [`Self::ID`] must identify that layout. +pub trait ExtCapability: FromBytes + IntoBytes { + /// PCI extended capability ID for this register layout. + const ID: ExtCapId; +} + +impl ConfigSpace<'_, Region<0>> { + /// Base offset of this capability in configuration space. + #[inline] + pub fn offset(&self) -> usize { + ConfigSpaceBackend::as_ptr(*self).addr() + } + + /// Size of this capability region in bytes. + #[inline] + pub fn size(&self) -> usize { + KnownSize::size(ConfigSpaceBackend::as_ptr(*self)) + } +} + +impl<'a> ConfigSpace<'a, Extended> { + /// Finds and projects an extended capability into its typed register layout. + /// + /// # Examples + /// + /// ```no_run + /// use kernel::pci; + /// + /// fn probe_sriov( + /// pdev: &pci::Device, + /// ) -> Result<(), kernel::error::Error> { + /// let sriov = pdev + /// .config_space_extended()? + /// .find_ext_capability::()?; + /// + /// let total_vfs = kernel::io_read!(sriov, .total_vfs); + /// let vf_offset = kernel::io_read!(sriov, .vf_offset); + /// kernel::io_write!(sriov, .num_vfs, 4u16); + /// let bar0 = sriov.read_vf_bar(0)?; + /// let bar1 = sriov.read_vf_bar(bar0.next_index())?; + /// + /// Ok(()) + /// } + /// ``` + pub fn find_ext_capability(&self) -> Result> { + let offset = usize::from( + // SAFETY: `self.pdev` is valid by the type invariant of `ConfigSpace`. + unsafe { + bindings::pci_find_ext_capability(self.pdev.as_raw(), i32::from(C::ID.as_raw())) + }, + ); + + if offset == 0 { + return Err(ENODEV); + } + + let size = self.calculate_ext_cap_size(offset); + + let base = ConfigSpaceBackend::as_ptr(*self) + .cast::() + .wrapping_add(offset); + let ptr = Region::<0>::ptr_try_from_raw_parts_mut(base, size)?; + + // SAFETY: `offset` was returned by `pci_find_ext_capability`, and + // `calculate_ext_cap_size` bounds `ptr` at the next capability or the end of the extended + // configuration space. `ptr_try_from_raw_parts_mut` verified the region layout. + let capability = unsafe { ConfigSpaceBackend::project_view(*self, ptr) }; + + capability.try_cast::() + } + + /// Calculates the size of the extended capability at `offset`. + /// + /// The capability extends to the next extended capability, or to the end of the extended + /// configuration space if it is the last one. `offset` must be a DWORD-aligned offset within + /// the extended configuration space returned by `pci_find_ext_capability`. If its header + /// cannot be read, the capability is treated as the last one. + fn calculate_ext_cap_size(&self, offset: usize) -> usize { + let header = self.try_read32(offset).unwrap_or(0); + // SAFETY: Pure bit manipulation, no preconditions. + // CAST: The next-cap pointer is a 12-bit field (max 0xFFC), always fits in `usize`. + let next = unsafe { bindings::pci_ext_cap_next(header) } as usize; + + if next > offset { + next - offset + } else { + (*self).size() - offset + } + } +} + +/// SR-IOV register layout per PCIe spec (64 bytes starting at cap offset). +#[repr(C)] +#[derive(FromBytes, IntoBytes)] +pub struct ExtSriovRegs { + /// Extended capability header. + pub header: u32, + /// SR-IOV capabilities. + pub cap: u32, + /// SR-IOV control. + pub ctrl: u16, + /// SR-IOV status. + pub status: u16, + /// Initial VFs. + pub initial_vfs: u16, + /// Total VFs. + pub total_vfs: u16, + /// Number of VFs. + pub num_vfs: u16, + /// Function dependency link. + pub func_dep_link: u16, + /// First VF offset. + pub vf_offset: u16, + /// VF stride. + pub vf_stride: u16, + _reserved: u16, + /// VF device ID. + pub vf_device_id: u16, + /// Supported page sizes. + pub supported_page_sizes: u32, + /// System page size. + pub system_page_size: u32, + /// VF BARs (BAR0–BAR5). + pub vf_bar: [u32; NUM_VF_BARS], + /// VF migration state array offset. + pub migration_state: u32, +} + +impl ExtCapability for ExtSriovRegs { + const ID: ExtCapId = ExtCapId::Sriov; +} + +/// A typed view of an SR-IOV extended capability. +pub type ExtSriovCapability<'a> = ConfigSpace<'a, ExtSriovRegs>; + +/// A decoded VF memory BAR. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ExtSriovVfBar { + address: u64, + is_64bit: bool, + next_index: usize, +} + +impl ExtSriovVfBar { + /// Returns the BAR address without PCI attribute bits. + #[inline] + pub fn address(&self) -> u64 { + self.address + } + + /// Returns whether the BAR is 64-bit. + #[inline] + pub fn is_64bit(&self) -> bool { + self.is_64bit + } + + /// Returns the configuration-space slot index of the next logical BAR. + #[inline] + pub fn next_index(&self) -> usize { + self.next_index + } +} + +impl ConfigSpace<'_, ExtSriovRegs> { + /// Reads and decodes the VF memory BAR at configuration-space slot `bar_index`. + #[inline] + pub fn read_vf_bar(&self, bar_index: usize) -> Result { + if bar_index >= NUM_VF_BARS { + return Err(EINVAL); + } + + let low = crate::io_read!(*self, .vf_bar[try: bar_index]); + if low & bindings::PCI_BASE_ADDRESS_SPACE != bindings::PCI_BASE_ADDRESS_SPACE_MEMORY { + return Err(EINVAL); + } + + let is_64bit = low & bindings::PCI_BASE_ADDRESS_MEM_TYPE_MASK + == bindings::PCI_BASE_ADDRESS_MEM_TYPE_64; + let following_index = bar_index.checked_add(1).ok_or(EINVAL)?; + + let (address, next_index) = if is_64bit { + if following_index >= NUM_VF_BARS { + return Err(EINVAL); + } + + let high = crate::io_read!(*self, .vf_bar[try: following_index]); + ( + (u64::from(high) << 32) | u64::from(low & !VF_MEMORY_BAR_ATTRIBUTE_BITS), + following_index.checked_add(1).ok_or(EINVAL)?, + ) + } else { + ( + u64::from(low & !VF_MEMORY_BAR_ATTRIBUTE_BITS), + following_index, + ) + }; + + Ok(ExtSriovVfBar { + address, + is_64bit, + next_index, + }) + } +} -- 2.53.0