Re: [PATCH v17 10/14] KVM: selftests: arm64: Add GCS registers to get-reg-list

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] GCS registers in `el2_regs` are inserted out of order compared to their system register encoding, violating the array's sorting convention.
--

--- Patch [10]: [PATCH v17 10/14] KVM: selftests: arm64: Add GCS registers to get-reg-list ---
commit 54610fb50b06e8daefb5c3cb9a29fbd4f7e9af9a
Author: Mark Brown <broonie@kernel.org>

KVM: selftests: arm64: Add GCS registers to get-reg-list

This commit adds the new Guarded Control Stack (GCS) registers to the
get-reg-list selftest for ARM64. It includes GCSCR_ELx, GCSCRE0_EL1, and
GCSPR_ELx in the validation arrays.

> diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testing/selftests/kvm/arm64/get-reg-list.c
> --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c
[ ... ]
> @@ -757,6 +767,8 @@ static __u64 el2_regs[] = {
>  	SYS_REG(PIRE0_EL2),
>  	SYS_REG(PIR_EL2),
>  	SYS_REG(POR_EL2),
> +	SYS_REG(GCSPR_EL2),
> +	SYS_REG(GCSCR_EL2),

[Severity: Low]
This isn't a bug, but are these registers inserted out of order compared to
their system register encoding?

The el2_regs array appears to be sorted by encoding (Op0, Op1, CRn, CRm,
Op2). Both GCSCR_EL2 (3, 4, 2, 5, 0) and GCSPR_EL2 (3, 4, 2, 5, 1) have
CRn=2, which suggests they should be placed earlier in the array, perhaps
near VTCR_EL2 or VNCR_EL2.

Also, should GCSCR_EL2 (Op2=0) precede GCSPR_EL2 (Op2=1) here to maintain
the correct relative ordering?

>  	SYS_REG(AMAIR_EL2),
>  	SYS_REG(VBAR_EL2),
>  	SYS_REG(CONTEXTIDR_EL2),

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260731-arm64-gcs-v17-0-5e39ca01b14e@kernel.org?part=10