[PATCH v5 06/31] arm64/sysreg: Convert SPSR_ELx to automatic register generation

[Steffen Eiden <seiden@linux.ibm.com>]

Convert SPSR_EL{1, 2, 12} to automatic register generation as per
DDIO616 2026-06. No functional change.

Signed-off-by: Steffen Eiden <seiden@linux.ibm.com>
---
 arch/arm64/include/asm/sysreg.h |  3 --
 arch/arm64/tools/sysreg         | 72 +++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4bfdac9401bd..1aa601c95188 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -295,7 +295,6 @@
 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
 
-#define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
 
 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
@@ -518,7 +517,6 @@
 #define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
 
 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
-#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
 #define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
 #define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)
@@ -604,7 +602,6 @@
 #define SYS_BRBCR_EL12			sys_reg(2, 5, 9, 0, 0)
 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
-#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7cb61aca3797..2a4b94e8c62f 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -401,6 +401,78 @@ Res0	3:1
 Field	0	SO
 EndSysreg
 
+Sysreg	SPSR_EL1	3	0	4	0	0
+Res0	63:37
+Field	36	UNIJ
+Res0	35:34
+Field	33	PPEND
+Res0	32
+Field	31	N
+Field	30	Z
+Field	29	C
+Field	28	V
+Field	27	Q
+Field	26:25	IT01
+Field	24	DIT
+Field	23	SSBS
+Field	22	PAN
+Field	21	SS
+Field	20	IL
+Field	19:16	GE
+Field	15:10	IT27
+Field	9	E
+Field	8	A
+Field	7	I
+Field	6	F
+Field	5	T
+Field	4	M4
+Enum	3:0	M
+	0b0000	EL0
+	0b0100	EL1t
+	0b0101	EL1h
+	0b1000	EL1tnv
+	0b1001	EL1hnv
+EndEnum
+EndSysreg
+
+Sysreg	SPSR_EL2	3	4	4	0	0
+Res0	63:37
+Field	36	UNIJ
+Res0	35:34
+Field	33	PPEND
+Res0	32
+Field	31	N
+Field	30	Z
+Field	29	C
+Field	28	V
+Field	27	Q
+Field	26:25	IT01
+Field	24	DIT
+Field	23	SSBS
+Field	22	PAN
+Field	21	SS
+Field	20	IL
+Field	19:16	GE
+Field	15:10	IT27
+Field	9	E
+Field	8	A
+Field	7	I
+Field	6	F
+Field	5	T
+Field	4	M4
+Enum	3:0	M
+	0b0000	EL0
+	0b0100	EL1t
+	0b0101	EL1h
+	0b1000	EL2t
+	0b1001	EL3h
+EndEnum
+EndSysreg
+
+Sysreg	SPSR_EL12	3	5	4	0	0
+Mapping	SPSR_EL1
+EndSysreg
+
 Sysreg ID_PFR0_EL1	3	0	0	1	0
 Res0	63:32
 UnsignedEnum	31:28	RAS
-- 
2.53.0