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[84.1.210.181]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1fd445432dsm549201266b.41.2026.08.03.06.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 06:23:11 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Tvrtko Ursulin , Natalie Vock Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 00/10] drm/amdgpu/gfx6: Use GFX IP block soft reset on GFX6 (v2) Date: Mon, 3 Aug 2026 15:22:59 +0200 Message-ID: <20260803132309.36326-1-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Fix up various things in the GFX6 code to prepare it to work with IP block soft reset. The main challenge was figuring out how to properly initialize the compute queues so that they work well after a reset, as well as realizing that on GFX6 the compute queues also have a PFP (as opposed to GFX7+ where PFP is a graphics only thing). There are also other minor fixes. Implement GFX6 IP block soft reset: just reset everything in the GFX IP block (instead of taking a guess at which parts need to be reset) to make it consistent, and also handle clock and power gating to make sure not to degrade GPU functionality after a GFX IP block soft reset. This improves current user experience on all GFX6 chips: On GFX6 dGPUs, the current GPU recovery method always clears the contents of VRAM, which means that a buggy (hanging) app can crash the whole graphical session, which is less than ideal. Using GFX IP block soft reset means that we can now move on from GFX hangs on dGPUs without crashing the whole system. Tested on the following chips: Tahiti (FirePro W9000, Radeon HD 7870 XT) Cape Verde (Radeon R7 450) Pitcairn (Radeon R9 270X) Oland (Radeon 430) Changes from v1 to v2: * Add more explanation to various patches * Drop patch that enables some IRQs * Drop VM flush changes (will be submitted separately) Timur Kristóf (10): drm/amdgpu/gfx6: Fixup emit_cntxcntl() drm/amdgpu/gfx6: Fixup emitting SWITCH_BUFFER packets drm/amdgpu/gfx6: Use PFP on the compute queues too drm/amdgpu/gfx6: Initialize compute rings before CP start drm/amdgpu/gfx6: Clean up rings during reset drm/amdgpu/gfx6: Execute CLEAR_STATE when initializing compute rings drm/amdgpu/gfx6: Adjust how harvested TCCs are set up drm/amdgpu/gfx6: Use COND_EXEC drm/amdgpu/gfx6: Add IP block soft reset implementation drm/amdgpu/gfx6: Enable IP block soft reset as a GPU recovery method drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 374 +++++++++++++----- .../include/asic_reg/gca/gfx_6_0_sh_mask.h | 32 +- 2 files changed, 295 insertions(+), 111 deletions(-) -- 2.55.0