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[84.1.210.181]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1fd445432dsm549201266b.41.2026.08.03.06.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 06:23:18 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Tvrtko Ursulin , Natalie Vock Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 07/10] drm/amdgpu/gfx6: Adjust how harvested TCCs are set up Date: Mon, 3 Aug 2026 15:23:06 +0200 Message-ID: <20260803132309.36326-8-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803132309.36326-1-timur.kristof@gmail.com> References: <20260803132309.36326-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Adjust gfx_v6_0_setup_tcc() to keep it working after a GFX IP block soft reset. On a soft reset, the TCP_CHAN_STEER_LO/HI registers are not cleared so the function needs a slight adjustment to how the number of active TCCs are calculated. Additionally, let's expose the disabled TCC mask in the tcc_disabled_mask field, like on other GPUs. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index b1dfcbe9640c..a51403caa342 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1597,7 +1597,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) */ static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) { - u32 i, tcc, tcp_addr_config, num_active_tcc = 0; + u32 i, tcc, tcp_addr_config, num_active_tcc = 0, num_max_active_tcc; u64 chan_steer, patched_chan_steer = 0; const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches; const u32 dis_tcc_mask = @@ -1611,6 +1611,8 @@ static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) if (!dis_tcc_mask) return; + num_max_active_tcc = num_max_tcc - hweight32(dis_tcc_mask); + /* Each 4-bit nibble contains the index of a TCC used by all TCPs */ chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); @@ -1623,9 +1625,12 @@ static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc); ++num_active_tcc; } + + if (num_active_tcc == num_max_active_tcc) + break; } - WARN_ON(num_active_tcc != num_max_tcc - hweight32(dis_tcc_mask)); + WARN_ON(num_active_tcc != num_max_active_tcc); /* Patch number of TCCs used by TCPs */ tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG), @@ -1635,6 +1640,8 @@ static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config); WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer)); WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); + + adev->gfx.config.tcc_disabled_mask = dis_tcc_mask; } static void gfx_v6_0_config_init(struct amdgpu_device *adev) -- 2.55.0