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Tsirkin" To: Sairaj Kodilkar Cc: Alejandro Jimenez , Ani Sinha , Eduardo Habkost , Igor Mammedov , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , qemu-devel@nongnu.org, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com Subject: Re: [PATCH 5/8] acpi_build: Introduce necessary macros and structs for AMD IOMMU IVRS Message-ID: <20260803175632-mutt-send-email-mst@kernel.org> References: <20260511123937.32743-1-sarunkod@amd.com> <20260511123937.32743-6-sarunkod@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260511123937.32743-6-sarunkod@amd.com> Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.811, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, May 11, 2026 at 06:09:34PM +0530, Sairaj Kodilkar wrote: > Introduce necessary macros, along with packed structs which represents > the AMD IVRS data structure, to hold the necessary information. This > will improve readability of the current code. > > Signed-off-by: Sairaj Kodilkar > Reviewed-by: Vasant Hegde > --- > hw/i386/acpi-build.h | 92 ++++++++++++++++++++++++++++++++++++++++++++ > hw/i386/amd_iommu.h | 6 +++ > 2 files changed, 98 insertions(+) > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > index 8ba3c33e4831..9fd60a186db1 100644 > --- a/hw/i386/acpi-build.h > +++ b/hw/i386/acpi-build.h > @@ -2,10 +2,102 @@ > #ifndef HW_I386_ACPI_BUILD_H > #define HW_I386_ACPI_BUILD_H > #include "hw/acpi/acpi-defs.h" > +#include "qemu/bitops.h" > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > void acpi_setup(void); > Object *acpi_get_i386_pci_host(void); > > +#define AMD_IVINFO_EFR_SUP BIT(0) > + > +#define AMD_IVHD_FLAG_HT_TUN_EN BIT(0) > +#define AMD_IVHD_FLAG_IOTLB_SUP BIT(4) > +#define AMD_IVHD_FLAG_PREF_SUP BIT(6) > +#define AMD_IVHD_FLAG_PPR_SUP BIT(7) > + > +#define AMD_IVHD_FEATURE_REPORT_XT_SUP_SHIFT (0) > +#define AMD_IVHD_FEATURE_REPORT_GT_SUP_SHIFT (2) > +#define AMD_IVHD_FEATURE_REPORT_GLX_SUP_SHIFT (3) > +#define AMD_IVHD_FEATURE_REPORT_GA_SUP_SHIFT (6) > +#define AMD_IVHD_FEATURE_REPORT_GATS_SHIFT (28) > +#define AMD_IVHD_FEATURE_REPORT_HATS_SHIFT (30) > + > +#define AMD_IVHD_ATTRIBUTES_HATDIS_SHIFT (0) > + > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_RESERVED (0) > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_ALL (1) > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_SELECT (2) > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_START_RANGE (3) > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_END_RANGE (4) > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_ALIAS_START_RANGE (0x43) > +#define AMD_IVHD_DEVICE_ENTRY_TYPE_SPECIAL_DEVICE (0x48) > + > +#define IVHD_VARIETY_IOAPIC (1) > +#define IVHD_VARIETY_HPET (2) > + > +/* > + * Vendor(AMD) specific fields in the IVRS header > + * Excludes fields in ACPI table header > + */ > +typedef > +struct AmdIvrsVendorHdr { > + uint32_t ivinfo; > + uint64_t reserved; > +} __attribute__((packed)) AmdIvrsVendorHdr; > + > +/* IVHD type 10h */ > +typedef > +struct AmdIvhdHdr10 { > + uint8_t type; > + uint8_t flags; > + uint16_t length; > + uint16_t devid; > + uint16_t capab_offset; > + uint64_t base_addr; > + uint16_t pci_seg; > + uint16_t iommu_info; > + uint32_t iommu_feature_report; > +} __attribute__((packed)) AmdIvhdHdr10; > + > +/* IVHD type 11h */ > +typedef > +struct AmdIvhdHdr11 { > + uint8_t type; > + uint8_t flags; > + uint16_t length; > + uint16_t devid; > + uint16_t capab_offset; > + uint64_t base_addr; > + uint16_t pci_seg; > + uint16_t iommu_info; > + uint32_t iommu_attributes; > + uint64_t efr; > + uint64_t efr2; > +} __attribute__((packed)) AmdIvhdHdr11; > + > +typedef > +struct AmdIvhdDeviceEntry { > + uint8_t type; > + uint16_t devid; > + uint8_t dte_setting; > +} __attribute__((packed)) AmdIvhdDeviceEntry; > + > +typedef > +struct AmdIvhdDeviceEntryExt { > + uint8_t type; > + uint16_t devid_a; > + uint8_t dte_setting; > + union { > + struct { > + uint8_t handle; > + uint16_t devid_b; > + uint8_t variety; > + } __attribute__((packed)); > + struct { > + uint32_t ext_dte_setting; > + } __attribute__((packed)); > + }; > +} __attribute__((packed)) AmdIvhdDeviceEntryExt; > + > #endif Pls do not do this is not how we build ACPI tables. It is completely impossible to match fields and structs to spec since it does not repeat it verbatim. Instead of all this write functions matching spec exactly. Examples: /* Table 104: IVHD Device Entry Type Codes (8-byte) */ build_append_int_noprefix(....) /* Handle */ build_append_int_noprefix(....) /* DevIDb */ build_append_int_noprefix(....) /* Variety */ Same with all these numbers they are used exactly once. Instead of a macro document in a comment: build_append_int_noprefix(.... (0x0 << 30 /* 00b = 4 levels HATS */) | ....) You must also find and document for each table the *earliest* spec that gives the features you are using and where it is in that spec. Why earliest? it gives people better idea which guests it can be compatible with. > diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h > index fe8f4a6cdc74..d97ddbd612dc 100644 > --- a/hw/i386/amd_iommu.h > +++ b/hw/i386/amd_iommu.h > @@ -175,9 +175,15 @@ > #define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, 48)) > > /* AMDVI paging mode */ > +#define AMDVI_GATS_MODE_SHIFT (12) > +#define AMDVI_GATS_MODE_MASK (3ULL << 12) > #define AMDVI_GATS_MODE (2ULL << 12) > +#define AMDVI_HATS_MODE_SHIFT (10) > +#define AMDVI_HATS_MODE_MASK (3ULL << 10) > #define AMDVI_HATS_MODE (2ULL << 10) > #define AMDVI_HATS_MODE_RESERVED (3ULL << 10) > +#define AMDVI_GLX_SUP_SHIFT (14) > +#define AMDVI_GLX_SUP_MASK (3ULL << 14) > > /* Page Table format */ > > -- > 2.34.1