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Tsirkin" To: Sairaj Kodilkar Cc: Alejandro Jimenez , Ani Sinha , Eduardo Habkost , Igor Mammedov , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , qemu-devel@nongnu.org, vasant.hegde@amd.com, suravee.suthikulpanit@amd.com Subject: Re: [PATCH 2/8] amd_iommu: update PA, GVA and VA size macros Message-ID: <20260803181045-mutt-send-email-mst@kernel.org> References: <20260511123937.32743-1-sarunkod@amd.com> <20260511123937.32743-3-sarunkod@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260511123937.32743-3-sarunkod@amd.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.811, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, May 11, 2026 at 06:09:31PM +0530, Sairaj Kodilkar wrote: > Current implemenation supports upto 64 bit IOVA and upto 52 bit PA. > Modify related macros so that guest can see right size. > > Signed-off-by: Sairaj Kodilkar > --- > hw/i386/acpi-build.c | 2 +- > hw/i386/amd_iommu.c | 2 +- > hw/i386/amd_iommu.h | 6 +++--- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 9446a9f862ca..e4ad01eec037 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1763,7 +1763,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, > */ > build_append_int_noprefix(table_data, > (1UL << 0) | /* EFRSup */ > - (40UL << 8), /* PASize */ > + AMDVI_PA_SIZE_52, > 4); > /* reserved */ If a macro repeats I'm fine with a define but you dropped spec matching comment, not good. #define AMDVI_PA_SIZE_52 (52UL << 8) /* PASize */ Will help reader find it in the spec. In fact: /* PASize: 011_0100b = 52 bits */ would be even better. Similarly, elsewhere. > build_append_int_noprefix(table_data, 0, 8); > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 789e09d6f2bc..7c52f9ade6e6 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -2450,7 +2450,7 @@ static void amdvi_pci_realize(PCIDevice *pdev, Error **errp) > 0xff000000); > pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); > pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, > - AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR); > + AMDVI_PA_SIZE_52 | AMDVI_GVA_SIZE_48 | AMDVI_VA_SIZE_64); > } > > static void amdvi_sysbus_reset(DeviceState *dev) > diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h > index 302ccca5121f..fe8f4a6cdc74 100644 > --- a/hw/i386/amd_iommu.h > +++ b/hw/i386/amd_iommu.h > @@ -245,9 +245,9 @@ > #define AMDVI_PAGE_SHIFT_4K 12 > #define AMDVI_PAGE_MASK_4K GENMASK64(63, 12) > > -#define AMDVI_MAX_GVA_ADDR (2UL << 5) > -#define AMDVI_MAX_PH_ADDR (40UL << 8) > -#define AMDVI_MAX_VA_ADDR (48UL << 15) > +#define AMDVI_GVA_SIZE_48 (2UL << 5) > +#define AMDVI_PA_SIZE_52 (52UL << 8) > +#define AMDVI_VA_SIZE_64 (64UL << 15) > > /* Completion Wait data size */ > #define AMDVI_COMPLETION_DATA_SIZE 8 > -- > 2.34.1