From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA305C55822 for ; Mon, 3 Aug 2026 20:08:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3844010E7AE; Mon, 3 Aug 2026 20:08:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PjMdb8ns"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E78210E7AE for ; Mon, 3 Aug 2026 20:08:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785787729; x=1817323729; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CwS9fHkTnM7JQq3329RHTjMV+cV7Er8Ekc+pDcVUk68=; b=PjMdb8nsPoHOtPxmwN0rbkx+Op66sN2IpE0x9ya+gV6HM1yrkae7JMTb 0uVOxZlGB+py6lrHABe33554222TQV+H1ZOgU1p9eauW5TJLTEqhwiIoF 0DAK72+qS1m31hfIz1L7e8OODxDy2585yU3aAtUkSn23DUAfUK+1QnsjR PUA7IVEN+VhlSzopv5UNl3kTf5VzFdn+dEfwLgdj99VLHjg1AAO1QkDx1 Cw15pAP7kXvFChX4qfz14cZCxQF+498P7ihuaqhnKzppdltE7zTkw/h2k lPkIZjYQYc4ZrKyWmIeRVd0FPPp/OluvtF1x+V68Bg2BniskEIABxQgdn w==; X-CSE-ConnectionGUID: ugmeCZXWQSen6Q9ZRiczGg== X-CSE-MsgGUID: b0WvVF9STVKFhJsUhmHm2w== X-IronPort-AV: E=McAfee;i="6800,10657,11864"; a="86188515" X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="86188515" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 13:08:49 -0700 X-CSE-ConnectionGUID: VZdakwgmRO6mkltQT9ek0g== X-CSE-MsgGUID: xMANrt27RTqmBg+VLl/6SQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="266433156" Received: from dut6094bmgfrd.fm.intel.com ([10.80.55.44]) by fmviesa005.fm.intel.com with ESMTP; 03 Aug 2026 13:08:49 -0700 From: Jia Yao To: intel-xe@lists.freedesktop.org Cc: Jia Yao , Gwan-gyeong Mun , Matthew Auld , stable@vger.kernel.org Subject: [PATCH v7 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX Date: Mon, 3 Aug 2026 20:08:37 +0000 Message-ID: <20260803200838.98826-3-jia.yao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803200838.98826-1-jia.yao@intel.com> References: <20260803200838.98826-1-jia.yao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO was previously created in system memory and later reallocated in xe_guc_realloc_post_hwconfig(). Allocate the UM queue BO directly in VRAM on dGFX, where it is ultimately required. Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement") Cc: Gwan-gyeong Mun Cc: Matthew Auld Cc: # v6.12+ Signed-off-by: Jia Yao --- drivers/gpu/drm/xe/xe_guc.c | 6 ------ drivers/gpu/drm/xe/xe_guc_ads.c | 17 ++++++++++------- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index 4f132bf8539d..4286bd05c686 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -732,12 +732,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) if (ret) return ret; - if (guc->ads.um_queue_bo) { - ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo); - if (ret) - return ret; - } - return 0; } diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index ef8e9cc35c8c..a69ec584cc0f 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -446,19 +446,22 @@ int xe_guc_ads_init(struct xe_guc_ads *ads) /* * Allocate a separate BO for the HW fault ring (UM queues). * - * Round the size up to the next power of two so that + * Round the size up to the next power of two so that on iGPU * (system memory, no IOMMU) the TTM pool issues a single * alloc_pages(order=N) call, maximising the chance of getting * a physically contiguous block. GuC requires contiguous DPA. */ - size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE * + size_t um_size = IS_DGFX(xe) ? + GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX : + roundup_pow_of_two(GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX); - bo = xe_managed_bo_create_pin_map(xe, tile, um_size, - XE_BO_FLAG_SYSTEM | - XE_BO_FLAG_GGTT | - XE_BO_FLAG_GGTT_INVALIDATE | - XE_BO_FLAG_PINNED_NORESTORE); + u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | + XE_BO_FLAG_GGTT | + XE_BO_FLAG_GGTT_INVALIDATE | + XE_BO_FLAG_PINNED_NORESTORE; + + bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags); if (IS_ERR(bo)) return PTR_ERR(bo); -- 2.43.0