From: sashiko-bot@kernel.org
To: "Mark Brown" <broonie@kernel.org>
Cc: "Oliver Upton" <oupton@kernel.org>,
kvmarm@lists.linux.dev, "Marc Zyngier" <maz@kernel.org>
Subject: Re: [PATCH v18 06/14] KVM: arm64: Validate GCS exception lock when emulating ERET
Date: Mon, 03 Aug 2026 23:41:44 +0000 [thread overview]
Message-ID: <20260803234145.48E161F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260803-arm64-gcs-v18-6-fd8c40f5ad88@kernel.org>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] kvm_check_illegal_exlock_return() incorrectly reads the host's physical GCSCR_EL1 register instead of the guest's virtual registers when emulating an ERET.
--
--- Patch [6]: [PATCH v18 06/14] KVM: arm64: Validate GCS exception lock when emulating ERET ---
commit 1a99244e8c449893f9c88233d42b775527985630
Author: Mark Brown <broonie@kernel.org>
KVM: arm64: Validate GCS exception lock when emulating ERET
This commit adds validation for a GCS-specific case where an illegal
exception return can be generated due to an EXLOCK mismatch, emulating this
behavior for nested guests.
> diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h
> index 012d711034d17..b2343f67d15b7 100644
> --- a/arch/arm64/include/asm/kvm_nested.h
> +++ b/arch/arm64/include/asm/kvm_nested.h
[ ... ]
> @@ -240,6 +240,45 @@ static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr)
> }
> #endif
>
> +#ifdef CONFIG_ARM64_GCS
> +/*
> + * A subset of the pseudocode ELFromSPSR(), validity checks are
> + * assumed to have been done in code that is not GCS specific.
> + */
> +static inline int exlock_el_from_spsr(u64 spsr)
> +{
> + return FIELD_GET(GENMASK(3, 2), spsr);
> +}
> +
> +/* See IllegalExceptionReturn() pseudocode */
> +static inline bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu,
> + u64 spsr)
> +{
> + u64 cur_el, target_el;
> +
> + if (!kvm_has_gcs(vcpu->kvm))
> + return false;
> +
> + if (vcpu->arch.ctxt.regs.pstate & PSR_EXLOCK_BIT)
> + return false;
> +
> + cur_el = exlock_el_from_spsr(vcpu->arch.ctxt.regs.pstate);
> + target_el = exlock_el_from_spsr(spsr);
> +
> + if (cur_el != target_el)
> + return false;
> +
> + return read_sysreg_el1(SYS_GCSCR) & GCSCR_ELx_EXLOCKEN;
[Severity: High]
Does this code read the host's physical GCSCR_EL1 hardware register instead
of the nested guest's virtual register?
When emulating an ERET for a nested guest, this validation is called in the
slow path:
kvm_check_illegal_exception_return()
kvm_check_illegal_exlock_return()
At this point, the world switch has already finished, meaning the physical
registers hold the host's state. Reading the physical SYS_GCSCR here will
cause the nested guest's ERET behavior to be evaluated against the host
userspace configuration, which might incorrectly trigger or miss architecturally
required exception injections.
Should this fetch the guest's virtual register via vcpu_read_sys_reg()
instead, depending on the value of cur_el?
> +}
> +
> +#else
> +static inline bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu,
> + u64 spsr)
> +{
> + return false;
> +}
> +#endif
[ ... ]
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index b32742d9dd73e..0f0723f22000a 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
[ ... ]
> @@ -2740,10 +2740,13 @@ static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
> * - trying to return to an illegal M value
> * - trying to return to a 32bit EL
> * - trying to return to EL1 with HCR_EL2.TGE set
> + * - GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK is 0 when attempting
> + * to return from ELx the same EL.
> */
> if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h ||
> mode == 0b00001 || (mode & BIT(1)) ||
> (spsr & PSR_MODE32_BIT) ||
> + kvm_check_illegal_exlock_return(vcpu, spsr) ||
> (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t ||
> mode == PSR_MODE_EL1h))) {
> u64 mask;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org?part=6
next prev parent reply other threads:[~2026-08-03 23:41 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-03 22:56 [PATCH v18 00/14] KVM: arm64: Provide guest support for GCS Mark Brown
2026-08-03 22:56 ` [PATCH v18 01/14] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Mark Brown
2026-08-03 22:56 ` [PATCH v18 02/14] KVM: arm64: Fix FGT mapping for HFGITR_EL2.nGCSEPP Mark Brown
2026-08-03 22:56 ` [PATCH v18 03/14] KVM: arm64: Manage GCS access and registers for guests Mark Brown
2026-08-03 23:31 ` sashiko-bot
2026-08-05 9:48 ` Yao Yuan
2026-08-05 12:32 ` Mark Brown
2026-08-06 6:51 ` Yao Yuan
2026-08-06 16:43 ` Mark Brown
2026-08-03 22:56 ` [PATCH v18 04/14] KVM: arm64: Ensure GCS memory effects are visible Mark Brown
2026-08-03 23:33 ` sashiko-bot
2026-08-06 8:25 ` Yao Yuan
2026-08-03 22:56 ` [PATCH v18 05/14] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Mark Brown
2026-08-06 10:30 ` Yao Yuan
2026-08-03 22:56 ` [PATCH v18 06/14] KVM: arm64: Validate GCS exception lock when emulating ERET Mark Brown
2026-08-03 23:41 ` sashiko-bot [this message]
2026-08-03 22:56 ` [PATCH v18 07/14] KVM: arm64: Forward GCS exceptions to nested guests Mark Brown
2026-08-03 22:56 ` [PATCH v18 08/14] KVM: arm64: Enforce EXLOCK for SPSR and ELR Mark Brown
2026-08-03 22:56 ` [PATCH v18 09/14] KVM: arm64: Allow GCS to be enabled for guests Mark Brown
2026-08-03 22:56 ` [PATCH v18 10/14] KVM: selftests: arm64: Add GCS registers to get-reg-list Mark Brown
2026-08-03 22:56 ` [PATCH v18 11/14] KVM: selftests: arm64: Add GCS to set_id_regs Mark Brown
2026-08-03 22:56 ` [PATCH v18 12/14] KVM: selftests: arm64: Only restore SPSR_EL1 and ELR_EL1 if they change Mark Brown
2026-08-03 22:56 ` [PATCH v18 13/14] tools: Synchronise the kernel esr.h Mark Brown
2026-08-03 22:56 ` [PATCH v18 14/14] KVM: selftests: arm64: Add GCS EXLOCK exception emulation test Mark Brown
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