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From: Amit Machhiwal <amachhiw@linux.ibm.com>
To: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Cc: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	Madhavan Srinivasan <maddy@linux.ibm.com>,
	Praveen K Pandey <praveen@linux.ibm.com>
Subject: Re: [PATCH v2 1/4] powerpc/pseries: Limit PVR list to 16 entries for CAS negotiation
Date: Tue, 4 Aug 2026 00:02:08 +0530	[thread overview]
Message-ID: <20260803235347.b630c20f-dc-amachhiw@linux.ibm.com> (raw)
In-Reply-To: <20260803155724.3272052-2-mahesh@linux.ibm.com>

On 2026/08/03 09:27 PM, Mahesh Salgaonkar wrote:
> Current Power system firmware caps the PVR list array size at 16 entries
> during CAS (Client Architecture Support) negotiation. Passing more than
> capped size to older firmware could cause an undefined behaviour and
> breaks compatibility.
> 
> Future Power system firmware releases will lift this restriction and
> support greater than 16 array entries.
> 
> Ensure that when running on Power11 or below hardware, the number
> of PVR entries passed during CAS negotiation does not exceed the
> firmware-imposed limit of 16.
> 
> In prom_send_capabilities(), compute start_index to skip the oldest
> leading pvrs[] entries when running on Power11 or below hardware, so
> that the pointer passed to ibm,client-architecture-support points to
> ibm_architecture_vec.pvrs[start_index], presenting exactly 16 entries to
> firmware.
> 
> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
> Tested-by: Praveen K Pandey <praveen@linux.ibm.com>
> ---
> Change in v2:
> - Define a named macro CAS_MAX_PVR_ENTRIES
> ---
>  arch/powerpc/kernel/prom_init.c | 35 ++++++++++++++++++++++++++-------
>  1 file changed, 28 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
> index 53503937de0ee..6b50870759fd9 100644
> --- a/arch/powerpc/kernel/prom_init.c
> +++ b/arch/powerpc/kernel/prom_init.c
> @@ -86,6 +86,12 @@
>   */
>  #define ADDR(x)		(u32)(unsigned long)(x)
>  
> +/*
> + * Current Power system firmware caps the PVR list array size at 16 entries
> + * during CAS (Client Architecture Support) negotiation.
> + */
> +#define CAS_MAX_PVR_ENTRIES	16
> +
>  #ifdef CONFIG_PPC64
>  #define OF_WORKAROUNDS	0
>  #else
> @@ -979,6 +985,10 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
>  			.mask = cpu_to_be32(0xfffe0000), /* POWER5/POWER5+ */
>  			.val  = cpu_to_be32(0x003a0000),
>  		},
> +		{
> +			.mask = cpu_to_be32(0xffffffff), /* all 2.04-compliant and earlier */
> +			.val  = cpu_to_be32(0x0f000001),
> +		},

It may be a good idea to add a comment (like below) above .pvrs = {
explaining why the oldest entries are at the front, otherwise the intent
of start_index trimming from the front is not obvious to future
contributors:

/*
 * The oldest/least-capable entries are placed at the FRONT so that
 * start_index trims them first when running on older firmware (Power11
 * and below) that caps the array at CAS_MAX_PVR_ENTRIES entries. As
 * newer processors are added, more old front entries will naturally
 * fall outside the firmware window. New entries must be inserted in
 * newest-first order AFTER these oldest front entries.
 */

>  		{
>  			.mask = cpu_to_be32(0xffff0000), /* POWER6 */
>  			.val  = cpu_to_be32(0x003e0000),
> @@ -1032,13 +1042,9 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
>  			.val  = cpu_to_be32(0x0f000003),
>  		},
>  		{
> -			.mask = cpu_to_be32(0xffffffff), /* all 2.05-compliant */
> +			.mask = cpu_to_be32(0xfffffffd), /* all 2.05-compliant */
>  			.val  = cpu_to_be32(0x0f000002),
>  		},
> -		{
> -			.mask = cpu_to_be32(0xfffffffe), /* all 2.04-compliant and earlier */
> -			.val  = cpu_to_be32(0x0f000001),
> -		},
>  	},
>  
>  	.num_vectors = NUM_VECTORS(6),
> @@ -1347,7 +1353,6 @@ static void __init prom_check_platform_support(void)
>  	};
>  	int prop_len = prom_getproplen(prom.chosen,
>  				       "ibm,arch-vec-5-platform-support");
> -

Nit: Looks unintentional whitespace change, please drop.

>  	/*
>  	 * First copy the architecture vec template
>  	 *
> @@ -1403,6 +1408,22 @@ static void __init prom_send_capabilities(void)
>  	ihandle root;
>  	prom_arg_t ret;
>  	u32 cores;
> +	int start_index = 0;
> +
> +	/*
> +	 * Ensure that when running on Power11 or below hardware, the number
> +	 * of PVR entries passed during CAS negotiation does not exceed the
> +	 * firmware-imposed limit of 16.
> +	 *
> +	 * Compute the start_index to skip the oldest leading pvrs[] entries
> +	 * when running on Power11 or below hardware, so that the pointer
> +	 * passed to ibm,client-architecture-support points to
> +	 * ibm_architecture_vec.pvrs[start_index], presenting exactly 16
> +	 * entries to firmware.
> +	 */
> +	if ((ARRAY_SIZE(ibm_architecture_vec_template.pvrs) > CAS_MAX_PVR_ENTRIES) &&
> +	    (PVR_VER(mfspr(SPRN_PVR)) <= PVR_POWER11))
> +		start_index = ARRAY_SIZE(ibm_architecture_vec_template.pvrs) - CAS_MAX_PVR_ENTRIES;
>  
>  	/* Check ibm,arch-vec-5-platform-support and fixup vec5 if required */
>  	prom_check_platform_support();
> @@ -1427,7 +1448,7 @@ static void __init prom_send_capabilities(void)
>  		if (call_prom_ret("call-method", 3, 2, &ret,
>  				  ADDR("ibm,client-architecture-support"),
>  				  root,
> -				  ADDR(&ibm_architecture_vec)) == 0) {
> +				  ADDR(&ibm_architecture_vec.pvrs[start_index])) == 0) {
>  			/* the call exists... */
>  			if (ret)
>  				prom_printf("\nWARNING: ibm,client-architecture"
> -- 
> 2.55.0
> 
> 


  reply	other threads:[~2026-08-03 18:31 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-03 15:57 [PATCH v2 0/4] Base support for Power12 Mahesh Salgaonkar
2026-08-03 15:57 ` [PATCH v2 1/4] powerpc/pseries: Limit PVR list to 16 entries for CAS negotiation Mahesh Salgaonkar
2026-08-03 18:32   ` Amit Machhiwal [this message]
2026-08-04  6:42     ` Mahesh J Salgaonkar
2026-08-03 15:57 ` [PATCH v2 2/4] powerpc: Add Power12 raw mode Mahesh Salgaonkar
2026-08-03 19:10   ` Amit Machhiwal
2026-08-04  5:52     ` Mahesh J Salgaonkar
2026-08-04  6:13       ` Amit Machhiwal
2026-08-03 15:57 ` [PATCH v2 3/4] powerpc: Add Power12 architected mode Mahesh Salgaonkar
2026-08-03 19:17   ` Amit Machhiwal
2026-08-04  6:00     ` Mahesh J Salgaonkar
2026-08-04  6:20       ` Amit Machhiwal
2026-08-05  9:32         ` Mahesh J Salgaonkar
2026-08-03 15:57 ` [PATCH v2 4/4] powerpc/perf: Add power12 Base Performance Monitoring support Mahesh Salgaonkar
2026-08-03 19:32   ` Amit Machhiwal
2026-08-04  6:34     ` Mahesh J Salgaonkar

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