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From: sashiko-bot@kernel.org
To: "Chaitanya Kumar Borah" <chaitanya.kumar.borah@intel.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [v6 9/9] drm/i915/color: Add color pipeline support for SDR planes
Date: Tue, 04 Aug 2026 13:29:20 +0000	[thread overview]
Message-ID: <20260804132921.D83F51F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260804123107.2256124-10-chaitanya.kumar.borah@intel.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

Pre-existing issues:
- [Critical] Use-After-Free vulnerability due to missing `drm_mode_object_unregister()` in `drm_colorop_cleanup()`.
- [High] Kernel crash via NULL pointer dereference if `kasprintf()` fails to allocate the pipeline name.
- [High] NULL pointer dereference of `colorop->dev` during error cleanup in `drm_colorop_cleanup()`.
- [High] Kernel crash via NULL pointer dereference when calling `list_del()` on an uninitialized `list_head`.
--

--- Patch [9]: [v6 9/9] drm/i915/color: Add color pipeline support for SDR planes ---
commit 80efc788f141365ff51bb15bb83bcb8d636605f2
Author: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

drm/i915/color: Add color pipeline support for SDR planes

This commit exposes the SDR plane color pipeline to user-space by
removing the restriction that previously limited it only to HDR planes.

> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 53e55ce0a5a35..38cfd6ed585d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -177,17 +177,11 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
>  
>  int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
>  {
[ ... ]
> -	/* Currently expose pipeline only for HDR planes */
> -	if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
> -		return 0;
> -
>  	/* Add pipeline consisting of transfer functions */
>  	ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);

[Severity: High]
This is a pre-existing issue, but does this function properly handle
memory allocation failures?

In drivers/gpu/drm/i915/display/intel_color_pipeline.c:
_intel_color_pipeline_plane_init(), the pipeline name is allocated:

	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d",
			       colorop[0]->base.base.id);

	return 0;

If kasprintf() fails, list->name is NULL, but the function still returns 0.
This NULL pointer is then passed up the stack and eventually to
drm_property_add_enum(), which calls strlen(name):

	if (WARN_ON(strlen(name) >= DRM_PROP_NAME_LEN))
		return -EINVAL;

Could this cause a NULL pointer dereference when memory is tight?


[Severity: High]
This is a pre-existing issue, but could error cleanup paths triggered during
initialization cause a NULL pointer dereference?

If intel_color_pipeline_plane_add_colorop() fails early (for example, if
drm_mode_object_add() fails), the cleanup path calls intel_colorop_destroy(),
which invokes drm_colorop_cleanup().

At this point, colorop->dev might still be NULL. In drm_colorop_cleanup():

	struct drm_device *dev = colorop->dev;
	struct drm_mode_config *config = &dev->mode_config;

	list_del(&colorop->head);
	config->num_colorop--;

Will this unconditionally dereference the NULL dev pointer?


[Severity: Critical]
This is a pre-existing issue, but is there a use-after-free risk when freeing
a colorop?

When a colorop is successfully added to the DRM IDR via drm_mode_object_add(),
it needs to be unregistered when destroyed. However, drm_colorop_cleanup()
does not appear to call drm_mode_object_unregister().

If a colorop is freed, but its mode object ID remains valid in the IDR, could
userspace trigger a use-after-free by interacting with the stale ID?


[Severity: High]
This is a pre-existing issue, but could the error handling crash when removing
an uninitialized list node?

In drm_plane_colorop_init(), if drm_mode_object_add() fails, the function
returns early before the colorop is added to the list:

	ret = drm_mode_object_add(dev, &colorop->base,
				  DRM_MODE_OBJECT_COLOROP);
	if (ret)
		return ret;

When the error path later calls drm_colorop_cleanup(), it unconditionally
executes list_del(&colorop->head). Since the head was zero-initialized via
kzalloc_obj(), __list_del() attempts to write to next->prev.

Will this result in an immediate NULL pointer dereference?

>  	if (ret)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804123107.2256124-1-chaitanya.kumar.borah@intel.com?part=9

  reply	other threads:[~2026-08-04 13:29 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04 12:30 [v6 0/9] drm/i915/color: Enable SDR plane color pipeline Chaitanya Kumar Borah
2026-08-04 12:30 ` [v6 1/9] drm/colorop: Add DRM_COLOROP_FIXED_MATRIX Chaitanya Kumar Borah
2026-08-04 12:31 ` [v6 2/9] drm/i915/color: Add CSC on SDR plane color pipeline Chaitanya Kumar Borah
2026-08-04 13:11   ` sashiko-bot
2026-08-04 12:31 ` [v6 3/9] drm/i915/display: extract glk_plane_color_ctl_input_csc helper Chaitanya Kumar Borah
2026-08-04 12:31 ` [v6 4/9] drm/i915/display: simplify glk_plane_color_ctl_input_csc Chaitanya Kumar Borah
2026-08-04 12:31 ` [v6 5/9] drm/i915/display: Program CSC on SDR planes based on Fixed Matrix Colorop Chaitanya Kumar Borah
2026-08-04 13:18   ` sashiko-bot
2026-08-04 12:31 ` [v6 6/9] drm/i915/color: Add support for 1D LUT in SDR planes Chaitanya Kumar Borah
2026-08-04 13:20   ` sashiko-bot
2026-08-04 12:31 ` [v6 7/9] drm/i915/color: Extract HDR post-CSC LUT programming to helper function Chaitanya Kumar Borah
2026-08-04 12:31 ` [v6 8/9] drm/i915/color: Program Plane Post CSC registers for SDR planes Chaitanya Kumar Borah
2026-08-04 12:31 ` [v6 9/9] drm/i915/color: Add color pipeline support " Chaitanya Kumar Borah
2026-08-04 13:29   ` sashiko-bot [this message]
2026-08-04 14:56 ` ✓ CI.KUnit: success for drm/i915/color: Enable SDR plane color pipeline (rev7) Patchwork
2026-08-04 15:32 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-08-05  0:12 ` ✓ Xe.CI.FULL: success " Patchwork
2026-08-05  2:24 ` ✓ i915.CI.BAT: " Patchwork
2026-08-05 14:15 ` ✓ i915.CI.Full: " Patchwork

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