From: sashiko-bot@kernel.org
To: "Ranjan Kumar" <ranjan.kumar@broadcom.com>
Cc: linux-scsi@vger.kernel.org
Subject: Re: [PATCH v4 02/10] mpi3mr: Update MPI Headers to revision 41
Date: Wed, 05 Aug 2026 11:33:04 +0000 [thread overview]
Message-ID: <20260805113305.C23AE1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260805110634.346670-3-ranjan.kumar@broadcom.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect shift macro definition `MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT` for mask `0x000c`.
--
--- Patch [2]: [PATCH v4 02/10] mpi3mr: Update MPI Headers to revision 41 ---
commit e227f986541dd8cdc45ad47d1ea7374c1b7cfc9c
Author: Ranjan Kumar <ranjan.kumar@broadcom.com>
mpi3mr: Update MPI Headers to revision 41
This commit updates the MPI headers to revision 41.
> diff --git a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
> index 33dd303c97bb5..7cf16a5c15b72 100644
> --- a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
> +++ b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
[ ... ]
> @@ -492,10 +498,31 @@ struct mpi3_man10_istwi_ctrlr_entry {
> };
>
> #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c)
> -#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000)
> -#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004)
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000)
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004)
> #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002)
> #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001)
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLITCH_FLTR_MASK (0xc000)
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLITCH_FLTR_SHIFT (14)
[ ... ]
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800)
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c)
> +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0)
[Severity: Low]
Is this shift value defined correctly?
The mask MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK is defined as 0x000c,
which covers bits 2 and 3. Should MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT
be 2 instead of 0 to ensure any future bitwise operations work properly?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260805110634.346670-1-ranjan.kumar@broadcom.com?part=2
next prev parent reply other threads:[~2026-08-05 11:33 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-05 11:06 [PATCH v4 00/10] mpi3mr: Few Enhancements and minor fixes Ranjan Kumar
2026-08-05 11:06 ` [PATCH v4 01/10] mpi3mr: Skip device shutdown during unload per controller configuration Ranjan Kumar
2026-08-05 11:33 ` sashiko-bot
2026-08-05 11:06 ` [PATCH v4 02/10] mpi3mr: Update MPI Headers to revision 41 Ranjan Kumar
2026-08-05 11:33 ` sashiko-bot [this message]
2026-08-05 11:06 ` [PATCH v4 03/10] mpi3mr: Add early timestamp synchronization after driver load Ranjan Kumar
2026-08-05 11:06 ` [PATCH v4 04/10] mpi3mr: Fix NVMe page size caching for non-operational devices Ranjan Kumar
2026-08-05 11:40 ` sashiko-bot
2026-08-05 11:06 ` [PATCH v4 05/10] mpi3mr: Fix performance regression caused by extended IRQ poll sleep Ranjan Kumar
2026-08-05 11:32 ` sashiko-bot
2026-08-05 11:06 ` [PATCH v4 06/10] mpi3mr: Fix memory leak on operational queue creation failure Ranjan Kumar
2026-08-05 11:40 ` sashiko-bot
2026-08-05 11:06 ` [PATCH v4 07/10] mpi3mr: Fix firmware event reference leak during cleanup Ranjan Kumar
2026-08-05 11:38 ` sashiko-bot
2026-08-05 11:06 ` [PATCH v4 08/10] mpi3mr: Fix SAS port allocation and registration error handling Ranjan Kumar
2026-08-05 11:40 ` sashiko-bot
2026-08-05 11:06 ` [PATCH v4 09/10] mpi3mr: Fix SAS PHY cleanup in host addition error paths Ranjan Kumar
2026-08-05 11:06 ` [PATCH v4 10/10] mpi3mr: Driver version update to 8.18.0.8.50 Ranjan Kumar
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