From: Dave Jiang <dave.jiang@intel.com>
To: inux-cxl@vger.kernel.org, linux-perf-users@vger.kernel.org
Cc: jic23@kernel.org, will@kernel.org, mark.rutland@arm.com,
dave@stgolabs.net, robin.murphy@arm.com, icheng@nvidia.com,
sashiko-bot@kernel.org,
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Subject: [PATCH v4 04/11] perf/cxl: Accept an overflow interrupt on MSI message number 0
Date: Wed, 5 Aug 2026 08:54:54 -0700 [thread overview]
Message-ID: <20260805155501.1294472-5-dave.jiang@intel.com> (raw)
In-Reply-To: <20260805155501.1294472-1-dave.jiang@intel.com>
cxl_pmu_probe() rejects the PMU when info->irq <= 0, but at that point the
field still holds the MSI/MSI-X message number the device signals overflow
on, not a Linux virq. That number is 0-based, and -1 means no interrupt
support. Message number 0 is valid and pci_irq_vector() takes a 0-based
index, so a compliant device signalling on the first vector fails to probe.
Reject only the no-interrupt case, matching how the CXL mailbox and event
interrupts handle it.
Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
Reported-by: sashiko-bot@kernel.org
Closes: https://sashiko.dev/#/patchset/20260715191454.459673-1-dave@stgolabs.net?part=1
Assisted-by: Claude:claude-opus-4-8
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Acked-by: Richard Cheng <icheng@nvidia.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v4:
- Move ahead of the info->msi_vec rename so this one-liner stands alone for
backporting (Robin).
---
drivers/perf/cxl_pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
index 40741e529d9b..2bebbbe67a0a 100644
--- a/drivers/perf/cxl_pmu.c
+++ b/drivers/perf/cxl_pmu.c
@@ -873,7 +873,7 @@ static int cxl_pmu_probe(struct device *dev)
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
- if (info->irq <= 0)
+ if (info->irq < 0)
return -EINVAL;
rc = pci_irq_vector(pdev, info->irq);
--
2.54.0
next prev parent reply other threads:[~2026-08-05 15:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-05 15:54 [PATCH v4 00/11] perf/cxlpmu: Misc sashiko raised issues fixes Dave Jiang
2026-08-05 15:54 ` [PATCH v4 01/11] perf/cxl: Program the requested event group on configurable counters Dave Jiang
2026-08-05 15:54 ` [PATCH v4 02/11] perf/cxl: Clear stale event fields before reprogramming a counter Dave Jiang
2026-08-05 16:07 ` sashiko-bot
2026-08-05 15:54 ` [PATCH v4 03/11] perf/cxl: Fix the counter overflow delta fixup Dave Jiang
2026-08-05 16:07 ` sashiko-bot
2026-08-05 15:54 ` Dave Jiang [this message]
2026-08-05 16:06 ` [PATCH v4 04/11] perf/cxl: Accept an overflow interrupt on MSI message number 0 sashiko-bot
2026-08-05 15:54 ` [PATCH v4 05/11] perf/cxl: Split the MSI vector out of info->irq Dave Jiang
2026-08-05 16:07 ` sashiko-bot
2026-08-05 15:54 ` [PATCH v4 06/11] cxl/pci: Add the PMUs after configuring events Dave Jiang
2026-08-05 15:54 ` [PATCH v4 07/11] perf/cxl: Don't share the overflow interrupt, and keep it pinned Dave Jiang
2026-08-05 15:54 ` [PATCH v4 08/11] perf/cxl: Unfreeze counters after handling an overflow interrupt Dave Jiang
2026-08-05 15:54 ` [PATCH v4 09/11] perf/cxl: Validate the hardware-reported counter width Dave Jiang
2026-08-05 15:55 ` [PATCH v4 10/11] perf/cxl: Don't log through pmu.dev in the overflow interrupt handler Dave Jiang
2026-08-05 16:16 ` sashiko-bot
2026-08-05 15:55 ` [PATCH v4 11/11] perf/cxl: Clear stale overflow status before using a counter Dave Jiang
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