From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, jani.nikula@linux.intel.com,
uma.shankar@intel.com, ville.syrjala@linux.intel.com,
suraj.kandpal@intel.com
Subject: [PATCH 01/44] drm/i915/hdmi: Parse frl max link rate from vbt
Date: Fri, 7 Aug 2026 09:43:46 +0530 [thread overview]
Message-ID: <20260807041430.229038-2-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20260807041430.229038-1-ankit.k.nautiyal@intel.com>
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Parse the maximum FRL link rate from VBT and store it for use
during FRL mode selection and link training.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 53 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 7 +++
3 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 97cbae2e547e..6354fa4041dc 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2734,6 +2734,43 @@ static bool is_port_valid(struct intel_display *display, enum port port)
return true;
}
+static int _intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data *devdata)
+{
+ struct intel_display *display = devdata->display;
+
+ if (display->vbt.version >= 237 &&
+ devdata->child.hdmi_max_frl_rate_valid) {
+ switch (devdata->child.hdmi_max_frl_rate) {
+ default:
+ case HDMI_MAX_FRL_RATE_PLATFORM:
+ drm_dbg_kms(display->drm,
+ "HDMI limited to support only TMDS modes\n");
+ return 0;
+ case HDMI_MAX_FRL_RATE_3G:
+ return 3000000;
+ case HDMI_MAX_FRL_RATE_6G:
+ return 6000000;
+ case HDMI_MAX_FRL_RATE_8G:
+ return 8000000;
+ case HDMI_MAX_FRL_RATE_10G:
+ return 10000000;
+ case HDMI_MAX_FRL_RATE_12G:
+ return 12000000;
+ }
+ }
+
+ /*
+ * When hdmi_max_frl_rate_valid is 0
+ * Don't consider the hdmi_max_frl_rate for
+ * limiting the FRL Rates on FRL-capable displays
+ */
+ if (display->vbt.version >= 237 &&
+ display->platform.meteorlake)
+ return 12000000;
+
+ return 0;
+}
+
static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
{
struct intel_display *display = devdata->display;
@@ -2741,6 +2778,7 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt;
int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
enum port port;
+ int hdmi_max_frl_rate;
port = intel_bios_encoder_port(devdata);
if (port == PORT_NONE)
@@ -2806,6 +2844,12 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
"Port %c VBT DP max link rate: %d\n",
port_name(port), dp_max_link_rate);
+ hdmi_max_frl_rate = _intel_bios_hdmi_max_frl_rate(devdata);
+ if (hdmi_max_frl_rate)
+ drm_dbg_kms(display->drm,
+ "VBT HDMI max frl rate for port %c: %d\n",
+ port_name(port), hdmi_max_frl_rate);
+
/*
* FIXME need to implement support for VBT
* vswing/preemph tables should this ever trigger.
@@ -3879,3 +3923,12 @@ void intel_bios_debugfs_register(struct intel_display *display)
debugfs_create_file("i915_vbt", 0444, display->drm->debugfs_root,
display, &intel_bios_vbt_fops);
}
+
+int intel_bios_hdmi_max_frl_rate(struct intel_encoder *encoder)
+{
+ struct intel_display *display = to_intel_display(encoder);
+ const struct intel_bios_encoder_data *devdata;
+
+ devdata = intel_bios_encoder_data_lookup(display, encoder->port);
+ return _intel_bios_hdmi_max_frl_rate(devdata);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 75dff27b4228..53d46c9fa6e1 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -102,6 +102,7 @@ int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata
void intel_bios_for_each_encoder(struct intel_display *display,
void (*func)(struct intel_display *display,
const struct intel_bios_encoder_data *devdata));
+int intel_bios_hdmi_max_frl_rate(struct intel_encoder *encoder);
void intel_bios_debugfs_register(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 0dc13d080e8a..db7484542dc0 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -381,6 +381,13 @@ struct bdb_general_features {
#define HDMI_MAX_DATA_RATE_340 4 /* 249+ */
#define HDMI_MAX_DATA_RATE_300 5 /* 249+ */
+#define HDMI_MAX_FRL_RATE_PLATFORM 0 /* 237 */
+#define HDMI_MAX_FRL_RATE_3G 1 /* 237 */
+#define HDMI_MAX_FRL_RATE_6G 2 /* 237 */
+#define HDMI_MAX_FRL_RATE_8G 3 /* 237 */
+#define HDMI_MAX_FRL_RATE_10G 4 /* 237 */
+#define HDMI_MAX_FRL_RATE_12G 5 /* 237 */
+
#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
/* DDC Bus DDI Type 155+ */
--
2.50.1
next prev parent reply other threads:[~2026-08-07 4:31 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-07 4:13 [PATCH 00/44] Enable HDMI FRL for MTL+ Ankit Nautiyal
2026-08-07 4:13 ` Ankit Nautiyal [this message]
2026-09-02 6:52 ` [PATCH 01/44] drm/i915/hdmi: Parse frl max link rate from vbt Kandpal, Suraj
2026-09-02 7:20 ` Jani Nikula
2026-08-07 4:13 ` [PATCH 02/44] drm/i915/hdmi: Add new data members for FRL configuration Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 03/44] drm/i915/hdmi: Add FRL link rate cap Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 04/44] drm/drm_scdc_helper: Add SCDC helper funcs for FRL Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 05/44] drm/i915/display: Add registers for HDMI FRL configuration Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 06/44] drm/i915/display: Add new members in crtc_state for " Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 07/44] drm/i915/intel_cx0_phy_regs: Add HDMI FRL SHIFT EN bit in PORT_BUF_CTL_1 Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 08/44] drm/i915/ddi: Update Transcoder/DDI registers with the frl bits Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 09/44] drm/i915/hdmi: Enable Scrambling only for TMDS mode Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 10/44] drm/i915/ddi: Simplify intel_ddi_enable() Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 11/44] drm/i915/ddi: Factor out common transcoder/vblank enable sequence Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 12/44] drm/i915/ddi: Update HDMI modeset sequence for MTL+ Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 13/44] drm/i915/hdmi: Add function to prepare registers for FRL mode Ankit Nautiyal
2026-08-07 4:13 ` [PATCH 14/44] drm/i915/hdmi: Add functions for FRL training state machine Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 15/44] drm/i915/intel_hdmi: Add helper to disable FRL Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 16/44] drm/i915/hdmi: Reduce FRL rate cap on rate change during training Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 17/44] drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 18/44] drm/i915/hdmi: Drive per-lane TxFFE during FRL link training Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 19/44] drm/i915/ltphy: Add PLL tables for HDMI FRL Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 20/44] drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 21/44] drm/i915/ltphy: Calculate port clock for HDMI FRL Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 22/44] drm/i915/ltphy: Verify HDMI FRL tables Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 23/44] drm/i915/ddi_buf: Add Vswing table for HDMI FRL Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 24/44] drm/i915/hdmi: Add provision for FRL mode while computing output format Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 25/44] drm/i915/hdmi: Rename port clock limit to specify tmds clock Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 26/44] drm/i915/cx0: Add helper to check if the FRL rate is valid Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 27/44] drm/i915/lt_phy: " Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 28/44] drm/i915/hdmi: Rename port clock valid to specify tmds clock Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 29/44] drm/i915/hdmi: Add FRL port and mode clock valid Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 30/44] drm/i915/hdmi_frl_dfm_regs: Define DFM registers Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 31/44] drm/i915/hdmi_frl_dfm: Define frl_dfm structure Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 32/44] drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 33/44] drm/i915/hdmi_frl_dfm: Add support for DFM calculation with DSC Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 34/44] drm/i915/hdmi: Add helper to write FRL CFG register Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 35/44] drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 36/44] drm/i915/hdmi_frl_dfm: Add function to compute FRL DFM config Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 37/44] drm/i915/hdmi: Add FRL clock computation based on DFM Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 38/44] drm/i915/hdmi: Add support for sending uevent to user for FRL training failure Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 39/44] drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 40/44] drm/i915/hdmi: Add read out for FRL state Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 41/44] drm/i915/hdmi_frl_dfm: Handle FRL Link M/N Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 42/44] drm/i915/display: Add FRL members to the state checker Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 43/44] drm/i915/hdmi: Compute output format for HDMI FRL mode Ankit Nautiyal
2026-08-07 4:14 ` [PATCH 44/44] drm/i915/hdmi: Enable FRL based mode clock valid Ankit Nautiyal
2026-08-07 4:42 ` ✗ CI.checkpatch: warning for Enable HDMI FRL for MTL+ Patchwork
2026-08-07 4:43 ` ✓ CI.KUnit: success " Patchwork
2026-08-07 5:21 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-07 15:32 ` ✓ i915.CI.BAT: " Patchwork
2026-08-07 17:04 ` ✗ Xe.CI.FULL: failure " Patchwork
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