From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v9 05/20] RISC-V: Define indirect CSR access helpers
Date: Fri, 07 Aug 2026 08:27:47 +0000 [thread overview]
Message-ID: <20260807082748.18CB31F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260807-counter_delegation-v9-5-58658104e487@meta.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The indirect CSR access macros use generic local variable names (`__flags`, `__value`, `__old_val`) which can silently shadow caller arguments, leading to logic corruption and unintended hardware writes.
--
--- Patch [5]: [PATCH v9 05/20] RISC-V: Define indirect CSR access helpers ---
commit abb666a0789f79a51327c355784dec21386f3bf0
Author: Atish Patra <atishp@rivosinc.com>
RISC-V: Define indirect CSR access helpers
The indirect CSR requires multiple instructions to read/write CSR. Add a few
helper macros for ease of usage.
Link: https://patch.msgid.link/20260701-counter_delegation-v8-5-7909f863a645@meta.com
> diff --git a/arch/riscv/include/asm/csr_indirect.h b/arch/riscv/include/asm/csr_indirect.h
> new file mode 100644
> index 0000000000000..0f558fac8f5f7
> --- /dev/null
> +++ b/arch/riscv/include/asm/csr_indirect.h
[ ... ]
> +#define csr_indirect_read(iregcsr, iselbase, iseloff) ({ \
> + unsigned long __value = 0; \
> + unsigned long __flags; \
[Severity: Medium]
Could these generic local variable names silently shadow caller arguments?
If a caller passes an expression using __flags or __value for iselbase or
iseloff, the macro's local variables will shadow them, potentially causing
the macro to use unintended values.
> + local_irq_save(__flags); \
> + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \
> + __value = csr_read(iregcsr); \
> + local_irq_restore(__flags); \
> + __value; \
> +})
> +
> +#define csr_indirect_write(iregcsr, iselbase, iseloff, value) ({ \
> + unsigned long __flags; \
[Severity: Medium]
Can this local __flags variable shadow the value argument if the caller
passes a variable named __flags?
If a caller executes csr_indirect_write(reg, base, off, __flags), the macro
would evaluate (value) using its own __flags variable (which holds the saved
IRQ state) instead of the caller's value. This would write the IRQ state to
the hardware CSR, potentially corrupting the CPU state.
> + local_irq_save(__flags); \
> + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \
> + csr_write(iregcsr, (value)); \
> + local_irq_restore(__flags); \
> +})
> +
> +#define csr_indirect_warl(iregcsr, iselbase, iseloff, warl_val) ({ \
> + unsigned long __old_val = 0, __value = 0; \
> + unsigned long __flags; \
[Severity: Medium]
Similar to the other macros, do these generic local variable names risk
shadowing the warl_val, iselbase, or iseloff arguments?
> + local_irq_save(__flags); \
> + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \
> + __old_val = csr_read(iregcsr); \
> + csr_write(iregcsr, (warl_val)); \
> + __value = csr_read(iregcsr); \
> + csr_write(iregcsr, __old_val); \
> + local_irq_restore(__flags); \
> + __value; \
> +})
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260807-counter_delegation-v9-0-58658104e487@meta.com?part=5
next prev parent reply other threads:[~2026-08-07 8:27 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-07 8:08 [PATCH v9 00/20] Add Counter delegation ISA extension support Atish Patra
2026-08-07 8:08 ` Atish Patra
2026-08-07 8:08 ` [PATCH v9 01/20] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-08-07 8:08 ` Atish Patra
2026-08-07 8:30 ` sashiko-bot
2026-08-07 8:08 ` [PATCH v9 02/20] RISC-V: Add Smcsrind and Sscsrind ISA extension CSR definitions Atish Patra
2026-08-07 8:08 ` Atish Patra
2026-08-07 8:08 ` [PATCH v9 03/20] RISC-V: Add Smcsrind and Sscsrind ISA extension definition and parsing Atish Patra
2026-08-07 8:08 ` Atish Patra
2026-08-07 8:08 ` [PATCH v9 04/20] dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptions Atish Patra
2026-08-07 8:08 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 05/20] RISC-V: Define indirect CSR access helpers Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:27 ` sashiko-bot [this message]
2026-08-07 8:09 ` [PATCH v9 06/20] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 07/20] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 08/20] RISC-V: Add Ssccfg extension CSR definition Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 09/20] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:25 ` sashiko-bot
2026-08-07 8:09 ` [PATCH v9 10/20] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 11/20] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 12/20] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:29 ` sashiko-bot
2026-08-07 8:09 ` [PATCH v9 13/20] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 14/20] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:34 ` sashiko-bot
2026-08-07 8:09 ` [PATCH v9 15/20] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 16/20] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:43 ` sashiko-bot
2026-08-07 8:09 ` [PATCH v9 17/20] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:40 ` sashiko-bot
2026-08-07 8:09 ` [PATCH v9 18/20] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:41 ` sashiko-bot
2026-08-07 8:09 ` [PATCH v9 19/20] tools/perf: Support event code for arch standard events Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-07 8:09 ` [PATCH v9 20/20] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-08-07 8:09 ` Atish Patra
2026-08-08 17:36 ` [PATCH v9 00/20] Add Counter delegation ISA extension support Paul Walmsley
2026-08-08 17:36 ` Paul Walmsley
2026-08-11 20:13 ` Atish Patra
2026-08-11 20:13 ` Atish Patra
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