From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D06E53BCD38; Fri, 7 Aug 2026 15:26:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786116392; cv=none; b=QOMcE5Fdl+w1uc6XHzR/qGOogWJanant/WyM+llioQmQNQMPfejBOnVDSX/gk5BtZt4e31EfoAelzkC3X0XlDd8k4nRQbSOYRuhnwgDIi+3lGnL/3LyaPc/I7L262ZbZZCpn901tiGoPyU67IxEJASM+QnKA4pWs2uSF3D02Og4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786116392; c=relaxed/simple; bh=VmqeSAaXGLmA4aP36SA25dqSOQQIYF6/TWaTeQVtoK4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YYKcIiTxk2KPlmFlRWh23ekV5LJWrB0EcMWQZssTfVG+s0rmzG6obh+m876XqNYlfCAG2dKLhl4YsgQruuZjpSVr9qWX88mNk2SSZaSseBvAdg1V5bR0Igam/Ef2DZlaK5LeNkeJyzBb2e67yKU61Yu2Fr4utZF1dZfAa9JX/pY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Wn0ZiJlZ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Wn0ZiJlZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 612951F000E9; Fri, 7 Aug 2026 15:26:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1786116390; bh=I9VKzsnz5omhFQ7q8EHnrCGFCS/IOvWjLAlb6ub85EY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Wn0ZiJlZrlJpCQYDBG1WUwpn97GqAstCnKP+X+PyNAgIhfluqcr1YPuq33DT8BZae r04W0duWxkVKYFdM8SqTU6XtWpcd0miSlN/T8mm4Gkl162tqI9Q1ab2g7HwFtF79fX 3KRn6wovmXOjfKr7lkjCiBbd8IIgJXSgo1U8SGqM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Nava kishore Manne , Radhey Shyam Pandey , Michal Simek , Vinod Koul Subject: [PATCH 6.6 160/261] phy: zynqmp: use read-modify-write for SERDES scrambler bypass Date: Fri, 7 Aug 2026 16:38:37 +0200 Message-ID: <20260807143418.819019927@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260807143415.358597922@linuxfoundation.org> References: <20260807143415.358597922@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Nava kishore Manne commit 21e0749f931702765b9d52d05740092bc87fcd8d upstream. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which performs a full register write, silently clearing any bits beyond the intended bypass control fields. Switch to xpsgtr_clr_set_phy() with clr=mask, set=mask to set only the bypass bits while preserving the remaining bits in each register. Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Cc: stable@vger.kernel.org Signed-off-by: Nava kishore Manne Signed-off-by: Radhey Shyam Pandey Acked-by: Michal Simek Link: https://patch.msgid.link/20260627155229.2791113-3-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/phy/xilinx/phy-zynqmp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -490,8 +490,12 @@ static void xpsgtr_lane_set_protocol(str /* Bypass (de)scrambler and 8b/10b decoder and encoder. */ static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy) { - xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER); - xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER); + xpsgtr_clr_set_phy(gtr_phy, L0_TM_DIG_6, + L0_TM_DIS_DESCRAMBLE_DECODER, + L0_TM_DIS_DESCRAMBLE_DECODER); + xpsgtr_clr_set_phy(gtr_phy, L0_TX_DIG_61, + L0_TM_DISABLE_SCRAMBLE_ENCODER, + L0_TM_DISABLE_SCRAMBLE_ENCODER); } /* DP-specific initialization. */