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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?38aYkC/uzdczRuIhkWjxYagt74EDJSrxSGBixlTnjq58lv40XggetCeMY4mO?= =?us-ascii?Q?NomPf1S3suxNPMKCiU0TakCdayPeEPYGnq5epOQragKshIQe2/iK4st2LY8U?= =?us-ascii?Q?xUoZVrY3WzpRQtH4Qqw5N/Cn+nEKN2kWqGMjIjfZ5CZtgsQTdTOwby+3guFW?= =?us-ascii?Q?DgorcQXrLokMTUGvWsA0GdU5r8hNcdUfcn0YsMa64RjvC6+ss9byS1+YmNa1?= =?us-ascii?Q?3Olh8fbGzzGpkdedb9ZnMK70CxBWYlYoSFElLkRVfI0uFEgC5ywA/7BVILZ4?= =?us-ascii?Q?eD0BxyU98rNTZF/WbagNiIY8LrqO+w7/2HdOGBEmlj8jVLEd7r1vP1JPn7pz?= =?us-ascii?Q?JrsE69AKJ1vvap+piTHC6dp4ZXoRhqPEwwlT2wSCAxz2A8qxy30zNiSckU9u?= =?us-ascii?Q?an8GB0lRmg8yrbxQlMAr8R2B99c4fiDiD6Mdu9O3sUcIeyUBXrIxfwxAtQ+u?= =?us-ascii?Q?Tb3XYkLqahCoizgRHF6JYE4yQHYk8LV9xGdy5pSB5sSqGtiHtyhksECtFuIZ?= =?us-ascii?Q?NRVOXu3FcOS4x3+tXTnFRiiEslzQkpauCMT+azytIwrmMa9E3vDfLocfympg?= =?us-ascii?Q?ZnYGXMuGKo6z++DzsoNDONg4ypy7ePrXvAxEGNFiww5UwCBl7KB7rR9N7ahP?= =?us-ascii?Q?8mLL11rpFz3pDUK/ISFBj9ehaf5R0M44Ko9zktvJORJoK7+eUtkmznBYDXkA?= =?us-ascii?Q?HoX7oTNXYrDA/qLt7MMwNAuQ1XDJzSX1/zIb7owNJB1wVmOon+IqpU163fRs?= =?us-ascii?Q?Sbh6vMtaSe4PtaOGs0TL1q9L220X0K1HTR6XgIJoOxOEc3BgjLui+LgECtm0?= =?us-ascii?Q?8lz4e8sa3V+UzDST4vvw3gi+s/p70TuuArv1/DBCQRynjzLNLipXd6MXcQdN?= =?us-ascii?Q?ZzCPNQpi3SYrMsoC33X8K8z1UGgXs5CrmyPQHwnP//aFKMXd3tNMl5cBwgOa?= =?us-ascii?Q?vaAKp7/vXeivv2ykpxwB74I4oS4ubEZNqYXhFkzY4E23rDTPSWmYauf6FYzC?= =?us-ascii?Q?DzNIfpx/WnFq9IufIs9mIdJHUy4chm2Vkm8TbgDyPApxCW6r2nDO7cTTalow?= =?us-ascii?Q?eNsj5Bi++lFL2UYzicwahp+zfiI/yc/oAncC7F26AkDOK2qpse/spSkdwK9P?= =?us-ascii?Q?HQYIS4QvtvTf6QWRP4qSe171Z1yOgHZ7jSJBpM9iP+FpIx8g/gcbIJsRKdr3?= =?us-ascii?Q?iHQMxkuLKG75EyClaoCY42mLq9OHwWUcfMJYTmGUr2KZKlT94mJ88W5UO5EQ?= =?us-ascii?Q?mM9LmOJVpRJfbDN0+YcK1YZVWt481W9EhmV9BWasYrhV+tntkeuKwMWYkmSe?= =?us-ascii?Q?P7o9WRY3MIMEXRMTkn1aa9ZN52sk1VwQMT0ESPqfYeBQKsU9b76P+DCAsewk?= =?us-ascii?Q?Ih4lwN+O06oQptmOLr8bjMJCQFuVhOM31WuutHF64CQJ/gVgughBlpHxldMZ?= =?us-ascii?Q?CRgZBn/EaIhNHBQf2XNs3oWOkJO5H7XgmVGbJC4l1rlySg3gPCWS0WxSU8RJ?= =?us-ascii?Q?ZkVS1+uJ40FEolTIH6YWgbkjNRa9z0p3B/QqHgj8aCXLcLXbkXOAmTZtYgSl?= =?us-ascii?Q?gIbkbSEGUfYIBTS+RQGFRGupbthV/w7/10dhtWlbP+3CITgvDvxR9uCXUw5d?= =?us-ascii?Q?oTbY9WYgPymj+wRIfU+sR6/LwzshmX0yUuMQpUBi6/9TQyFsVeo6Oe3PTKgQ?= =?us-ascii?Q?COXZk4vJFA+maT2LY++6T55dZpPhFMRF523NxeT1LQkjNcpup4ryR6a8e98n?= =?us-ascii?Q?Gbkjc4JiOg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1754a4e0-3821-4947-e2e6-08def4fabb4e X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2026 03:11:25.6008 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GtNzy2JH07wz8oQPbayPc3iMbpym4Ce8RSTxM8C9zC8meBOKFD6xXuzRfucEdDNQzcACrBOI+py6vl+ldVithA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4198 A PCI driver can accept INTx, MSI, or MSI-X, and how it acknowledges an interrupt can depend on which one the PCI core picks. The Rust abstraction never reported the choice, so a driver had to assume, and of course a wrong assumption would lead to a broken interrupt delivery setup. Report the type that the PCI core selected. Assisted-by: Cursor:claude-opus-5 Signed-off-by: John Hubbard --- rust/helpers/pci.c | 11 +++++++++++ rust/kernel/pci/irq.rs | 30 ++++++++++++++++++++++++++---- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c index 4ebf256dff23..87ccd0cec69f 100644 --- a/rust/helpers/pci.c +++ b/rust/helpers/pci.c @@ -24,6 +24,17 @@ __rust_helper bool rust_helper_dev_is_pci(const struct device *dev) return dev_is_pci(dev); } +__rust_helper unsigned int rust_helper_pci_irq_type(struct pci_dev *pdev) +{ + if (pdev->msix_enabled) + return PCI_IRQ_MSIX; + + if (pdev->msi_enabled) + return PCI_IRQ_MSI; + + return PCI_IRQ_INTX; +} + #ifndef CONFIG_PCI_IOV __rust_helper unsigned int rust_helper_pci_sriov_get_totalvfs(struct pci_dev *pdev) diff --git a/rust/kernel/pci/irq.rs b/rust/kernel/pci/irq.rs index 66723a43491b..10c728cd139e 100644 --- a/rust/kernel/pci/irq.rs +++ b/rust/kernel/pci/irq.rs @@ -100,11 +100,12 @@ fn from(vector: IrqVector<'a>) -> Self { /// /// # Invariants /// -/// `dev` has an allocation of `count` interrupt vectors. +/// `dev` has an allocation of `count` interrupt vectors of type `irq_type`. #[derive(Clone, Copy)] pub struct IrqAllocation<'a> { dev: &'a Device, count: NonZero, + irq_type: IrqType, } impl<'a> IrqAllocation<'a> { @@ -115,6 +116,15 @@ pub fn count(&self) -> NonZero { self.count } + /// Returns the interrupt type the PCI core selected. + /// + /// [`Device::alloc_irq_vectors`] takes a set of acceptable types and picks one of them, so a + /// driver whose behavior depends on the type asks for it here rather than assuming. Every + /// vector of the allocation has this type. + pub fn irq_type(&self) -> IrqType { + self.irq_type + } + /// Resolves the vector at `index` to the Linux IRQ number that delivers it. /// /// # Errors @@ -177,9 +187,21 @@ fn register<'a>( // `pci_alloc_irq_vectors` returns the number of vectors it allocated. let count = NonZero::new(ret as u32).ok_or(EINVAL)?; - // INVARIANT: `pci_alloc_irq_vectors` allocated `count` vectors for `dev`, numbered - // from 0. - let vectors = IrqAllocation { dev, count }; + // SAFETY: `dev.as_raw()` is a valid pointer to a `struct pci_dev`. + let irq_type = match unsafe { bindings::pci_irq_type(dev.as_raw()) } { + bindings::PCI_IRQ_MSIX => IrqType::MsiX, + bindings::PCI_IRQ_MSI => IrqType::Msi, + // The helper returns `PCI_IRQ_INTX` when neither MSI nor MSI-X is enabled. + _ => IrqType::Intx, + }; + + // INVARIANT: `pci_alloc_irq_vectors` allocated `count` vectors of `irq_type` for `dev`, + // numbered from 0. + let vectors = IrqAllocation { + dev, + count, + irq_type, + }; // INVARIANT: The IRQ vector allocation for `dev` above was successful. let irq_vecs = Self { dev: dev.into() }; -- 2.55.0