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[174.21.93.59]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbe8f19ace6sm2998102a12.2.2026.08.09.15.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 15:35:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org Subject: [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Date: Sun, 9 Aug 2026 15:34:56 -0700 Message-ID: <20260809223545.730664-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260809223545.730664-1-richard.henderson@linaro.org> References: <20260809223545.730664-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Since 758dce9c98a, the only possible values for instruction length are 2 and 4. Signed-off-by: Richard Henderson --- disas/riscv.h | 2 +- disas/riscv.c | 12 +++--------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/disas/riscv.h b/disas/riscv.h index 91ada8b531..eabe193b4f 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -11,7 +11,7 @@ /* types */ -typedef uint64_t rv_inst; +typedef uint32_t rv_inst; typedef uint16_t rv_opcode; /* enums */ diff --git a/disas/riscv.c b/disas/riscv.c index e3fbc26626..012f90fce6 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -5491,10 +5491,8 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, return format_inst(24, &dec); } -#define INST_FMT_2 "%04" PRIx64 " " -#define INST_FMT_4 "%08" PRIx64 " " -#define INST_FMT_6 "%012" PRIx64 " " -#define INST_FMT_8 "%016" PRIx64 " " +#define INST_FMT_2 "%04x " +#define INST_FMT_4 "%08x " static int print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) @@ -5530,12 +5528,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) case 4: (*info->fprintf_func)(info->stream, INST_FMT_4, inst); break; - case 6: - (*info->fprintf_func)(info->stream, INST_FMT_6, inst); - break; default: - (*info->fprintf_func)(info->stream, INST_FMT_8, inst); - break; + g_assert_not_reached(); } } -- 2.43.0