[PATCH v2 4/5] clocksource: mips-gic-timer: Set next GIC event on the correct VP

["Benoît Monin" <benoit.monin@bootlin.com>]

gic_next_event() programs the next event on the clock_event_device's target
CPU. When that CPU is not the current one, the compare register is reached
through the GIC VO (other/redirect) window, which is first pointed at the
target VP with write_gic_vl_other().

On a multi-cluster system each cluster has its own GIC. The VO window of
the local GIC is what write_gic_vl_other() redirects, so when the target
CPU belongs to another cluster, write_gic_vo_compare() lands in the
wrong GIC, overwriting the COMPARE register of a VP in the local cluster.

Redirect the core-other region to the target CPU's GIC local block
with mips_cm_lock_other_cpu() using CM_GCR_Cx_OTHER_BLOCK_LOCAL before
writing GIC_VO_COMPARE, and release it with mips_cm_unlock_other()
afterwards. This ensures that the correct VP is accessed in all cases.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clocksource/mips-gic-timer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index a1669266c94d..ddbb2f827bf0 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -61,8 +61,9 @@ static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
 	if (cpu == raw_smp_processor_id()) {
 		write_gic_vl_compare(cnt);
 	} else {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+		mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 		write_gic_vo_compare(cnt);
+		mips_cm_unlock_other();
 	}
 	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
 	return res;

-- 
2.55.0