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Mon, 10 Aug 2026 05:45:20 -0700 (PDT) Received: from DE-PF5B95TD.embedded.cmblu.dev ([87.129.199.250]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080c910aesm391823266b.30.2026.08.10.05.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 05:45:19 -0700 (PDT) From: Wadim Mueller To: Bin Meng Cc: qemu-devel@nongnu.org, philmd@linaro.org, qemu-block@nongnu.org Subject: Re: [PATCH] hw/sd/sdhci: complete non-interrupt ADMA descriptor chains in one pass Date: Mon, 10 Aug 2026 14:45:14 +0200 Message-ID: <20260810124519.34501-1-wafgo01@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20260804081459.8007-1-wafgo01@gmail.com> <20260805080540.323431-1-wafgo01@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=wafgo01@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Bin, Thanks for the 513930 pointer -- that was exactly the missing piece, and it changes my earlier result, so let me correct the record first. With "hw/sd: sdhci: Fix SDMA boundary bug" (513930) applied first, series 515264 builds on my tree (I applied 513930 patch 1 + 515264 patches 07-12; I dropped 13/26 "keep high-capacity memory blocks at 512" -- it didn't apply on my older hw/sd/sd.c and is orthogonal to the ADMA path). Re-running the same AM64x reproducer, 15 hands-off boots each: baseline (before either change): 7/15 time out your series (513930 + 515264 07-12): 0/15 my patch (complete non-INT chains in a pass): 0/15 So your series *does* fix the AM64x case -- my earlier "10/15" number was from my crude hand-approximation of patch 12 alone on the old base, which (as I feared) simply wasn't representative. Apologies for the noise; the real series resolves it here, same as my patch. As promised, the reproducer -- I kept it free of any proprietary bits: - The machine is public in my QEMU fork: https://github.com/wafgo/qemu branch cmblu/corenode (an "am64-virt" TI AM64x board). Build qemu-system-aarch64 from it; to observe the original failure, revert my fix commit cad8b499 ("fix(sdhci): complete non-int adma chains in one pass"). - A small image-free qtest on that branch, tests/qtest/am64-adma-pacing-test.c, drives an ADMA2 read on am64-virt and counts how many SDHC_TRANSFER_DELAY virtual-clock steps the chain takes to complete: 0 with either fix in place, >0 (the sliced, timer-paced transfer) without. It reproduces the *mechanism* deterministically, no guest image needed. Since your series fixes this, my standalone patch is effectively superseded -- please feel free to drop it in favour of 515264, I don't think a separate fix is needed. The one thing possibly worth keeping is the pacing regression test. As written it targets my fork's am64-virt, so it isn't directly mainline-able; if a test that catches this ADMA virtual-clock pacing would be useful upstream, I'd be glad to port it to an in-tree SDHCI machine -- e.g. the Icicle Kit where you hit the same "Timeout for status update", or the xilinx-zynq SDHCI you just added a test for in 513930. Would that be worthwhile, and which board would you prefer? Thanks again for the help, Wadim