Re: [PATCH 2/4] drm/imx: ipuv3-plane: add the pixel blend mode property

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Plane atomic update callback calls functions that acquire a sleeping lock (mutex).
--

--- Patch [2]: [PATCH 2/4] drm/imx: ipuv3-plane: add the pixel blend mode property ---
commit 166d0e9ef492a9f6b268953776bb8c6c929a2acc
Author: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

drm/imx: ipuv3-plane: add the pixel blend mode property

This commit adds a pixel blend mode property to IPUv3 planes. It configures
the planes to support coverage or none based on whether they are part of a
DP flow, and uses this blend mode to decide between global and per-pixel
alpha during plane updates.

> diff --git a/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c
> index a0fd39eebbbc2..bde5892264f4a 100644
> --- a/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c
> +++ b/drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

[ ... ]

> @@ -593,8 +621,8 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
>  	case IPU_DP_FLOW_SYNC_BG:
>  		if (new_state->normalized_zpos == 1) {
>  			ipu_dp_set_global_alpha(ipu_plane->dp,
> -						!fb->format->has_alpha, 0xff,
> -						true);
> +						!ipu_plane_use_pixel_alpha(new_state),
> +						0xff, true);

[Severity: High]
This isn't a bug introduced by this patch, but is it safe to call
ipu_dp_set_global_alpha() from the atomic update callback?

The DRM core invokes ipu_plane_atomic_update() in an atomic context
where sleeping is forbidden. However, ipu_dp_set_global_alpha()
unconditionally acquires a sleeping lock:

drivers/gpu/ipu-v3/ipu-dp.c:ipu_dp_set_global_alpha() {
	...
	mutex_lock(&priv->mutex);
	...
}

Could this trigger kernel warnings or deadlocks if the thread is scheduled
out while executing in a non-blocking DRM atomic commit phase?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260810-imx53-fix-hdmi-v1-0-fff9b1b17f25@oss.qualcomm.com?part=2