From: Mikail Sadic <mikail.sadic@ibm.com>
To: clg@kaod.org, peter.maydell@linaro.org
Cc: Mikail Sadic <mikail.sadic@ibm.com>,
pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com,
jeuk20.kim@samsung.com, philmd@mailo.com,
steven_lee@aspeedtech.com, leetroy@gmail.com,
jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com,
andrew@codeconstruct.com.au, joel@jms.id.au,
calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v3 4/8] i2c/aspeed: Fix DMA receive first-byte handling for block reads
Date: Mon, 10 Aug 2026 13:57:42 -0500 [thread overview]
Message-ID: <20260810185748.1253-5-mikail.sadic@ibm.com> (raw)
In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com>
An SMBus block read (I2C_M_RECV_LEN) reads the block length from the
first received byte. The Linux/U-Boot aspeed I2C driver obtains that
first byte from the I2CC_STS_AND_BUFF register (modelled here as
reg_byte_buf), even when the transfer uses DMA. The DMA receive path,
however, only wrote received data to DRAM and never updated
reg_byte_buf, so block reads read a stale/zero length.
Mirror the first DMA-received byte into reg_byte_buf so that
I2C_M_RECV_LEN transfers using DMA report the correct block length.
This is required for the ucd9000 driver, which uses
i2c_smbus_read_block_data().
Signed-off-by: Mikail Sadic <mikail.sadic@ibm.com>
---
hw/i2c/aspeed_i2c.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 27afcaecee..facb54d27e 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -365,6 +365,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus);
uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
+ bool first_dma_byte;
int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl,
RX_SIZE) + 1;
@@ -391,6 +392,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
}
aspeed_i2c_set_rx_dma_dram_offset(bus);
+ first_dma_byte = true;
while (bus->regs[reg_dma_len]) {
MemTxResult result;
@@ -407,6 +409,11 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
return;
}
+ /* Mirror first byte to reg_byte_buf for I2C_M_RECV_LEN. */
+ if (first_dma_byte) {
+ SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data);
+ first_dma_byte = false;
+ }
bus->dma_dram_offset++;
bus->regs[reg_dma_len]--;
/* In new mode, keep track of how many bytes we RXed */
--
2.53.0
next prev parent reply other threads:[~2026-08-10 18:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 18:57 [PATCH v3 0/8] Add IBM Huygens BMC machine for AST2700 Mikail Sadic
2026-08-10 18:57 ` [PATCH v3 1/8] fsi/cfam: Add common CFAM base class Mikail Sadic
2026-08-11 13:36 ` Miles Glenn
2026-08-10 18:57 ` [PATCH v3 2/8] fsi/cfam: Add CFAM-S model Mikail Sadic
2026-08-10 18:57 ` [PATCH v3 3/8] arm/aspeed: Wire AST2700 FSI controllers to APB-to-OPB bridges Mikail Sadic
2026-08-11 4:32 ` Cédric Le Goater
2026-08-10 18:57 ` Mikail Sadic [this message]
2026-08-11 4:30 ` [PATCH v3 4/8] i2c/aspeed: Fix DMA receive first-byte handling for block reads Cédric Le Goater
2026-08-11 7:33 ` Jamin Lin
2026-08-10 18:57 ` [PATCH v3 5/8] hw/sensor: Add UCD90320 model Mikail Sadic
2026-08-10 18:57 ` [PATCH v3 6/8] ufs: Make the logical block size configurable and answer absent LUNs Mikail Sadic
2026-08-10 18:57 ` [PATCH v3 7/8] ufs/aspeed: Add AST2700 UFS host controller Mikail Sadic
2026-08-10 18:57 ` [PATCH v3 8/8] arm/aspeed: Add AST2700 Huygens machine Mikail Sadic
2026-08-11 4:35 ` Cédric Le Goater
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