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Tue, 11 Aug 2026 03:10:32 +0000 From: Jamin Lin To: =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Eric Blake , Markus Armbruster , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: Jamin Lin , Troy Lee Subject: [PATCH v3 04/16] hw/misc/aspeed_hace: Support the CTR mode for the crypto command Thread-Topic: [PATCH v3 04/16] hw/misc/aspeed_hace: Support the CTR mode for the crypto command Thread-Index: AQHdKT74xMqUG90vmE2UC8cAwlWCGg== Date: Tue, 11 Aug 2026 03:10:32 +0000 Message-ID: <20260811031025.2784489-5-jamin_lin@aspeedtech.com> References: <20260811031025.2784489-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260811031025.2784489-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The AST2600, AST1030 and later crypto engines add AES/DES/3DES CTR mode=0A= (HACE10[6:4] =3D 0b100) on top of the ECB/CBC modes shared with the=0A= AST2500. Decode the CTR selection, round the working buffers up to a=0A= whole block so the stream-like final block is still processed a block at=0A= a time, and write the counter advanced by the number of blocks consumed=0A= back to the context buffer so the driver can continue across requests.=0A= =0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: Kane Chen =0A= ---=0A= hw/misc/aspeed_hace.c | 50 ++++++++++++++++++++++++++++++++++++++-----=0A= 1 file changed, 45 insertions(+), 5 deletions(-)=0A= =0A= diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c=0A= index 646ff50476..d84f7f9cec 100644=0A= --- a/hw/misc/aspeed_hace.c=0A= +++ b/hw/misc/aspeed_hace.c=0A= @@ -41,6 +41,7 @@=0A= #define CRYPT_CMD_OP_MODE_MASK (0x7 << 4)=0A= #define CRYPT_CMD_ECB (0x0 << 4)=0A= #define CRYPT_CMD_CBC (0x1 << 4)=0A= +#define CRYPT_CMD_CTR (0x4 << 4)=0A= /* AES key length HACE10[3:2] */=0A= #define CRYPT_CMD_AES_KEY_LEN_MASK (0x3 << 2)=0A= #define CRYPT_CMD_AES256 (0x2 << 2)=0A= @@ -587,6 +588,9 @@ static bool crypt_decode_cmd(uint32_t cmd, QCryptoCiphe= rAlgo *alg,=0A= case CRYPT_CMD_CBC:=0A= *mode =3D QCRYPTO_CIPHER_MODE_CBC;=0A= break;=0A= + case CRYPT_CMD_CTR:=0A= + *mode =3D QCRYPTO_CIPHER_MODE_CTR;=0A= + break;=0A= default:=0A= return false;=0A= }=0A= @@ -650,6 +654,22 @@ static bool crypt_prepare_sg(AspeedHACEState *s, uint6= 4_t addr,=0A= return copied =3D=3D len;=0A= }=0A= =0A= +/*=0A= + * Add @add to the big-endian counter block @ctr (@len bytes) in place, so= the=0A= + * CTR mode counter can be advanced by the number of blocks just consumed.= =0A= + */=0A= +static void crypt_be_add(uint8_t *ctr, size_t len, uint64_t add)=0A= +{=0A= + size_t i =3D len;=0A= +=0A= + while (i > 0 && add) {=0A= + i--;=0A= + add +=3D ctr[i];=0A= + ctr[i] =3D add & 0xff;=0A= + add >>=3D 8;=0A= + }=0A= +}=0A= +=0A= /*=0A= * Perform an AES/DES/3DES ECB/CBC operation. The source and destination a= re=0A= * either single contiguous buffers (direct access mode) or scatter-gather= =0A= @@ -675,6 +695,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd)=0A= uint64_t dst_addr;=0A= size_t iv_offset;=0A= size_t blocklen;=0A= + size_t buf_len;=0A= size_t keylen;=0A= bool status;=0A= =0A= @@ -727,8 +748,14 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd)=0A= return;=0A= }=0A= =0A= - src_buf =3D g_malloc0(len);=0A= - dst_buf =3D g_malloc0(len);=0A= + /*=0A= + * Round the working buffers up to a whole block. Block modes are alre= ady=0A= + * block-aligned; the stream-like CTR mode may leave a partial final b= lock=0A= + * that the engine still processes a full block at a time.=0A= + */=0A= + buf_len =3D QEMU_ALIGN_UP(len, blocklen);=0A= + src_buf =3D g_malloc0(buf_len);=0A= + dst_buf =3D g_malloc0(buf_len);=0A= =0A= /* Gather the source into the bounce buffer, per the selected mode. */= =0A= src_addr =3D s->regs[R_CRYPT_SRC];=0A= @@ -749,7 +776,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd)=0A= }=0A= =0A= if (encrypt) {=0A= - if (qcrypto_cipher_encrypt(cipher, src_buf, dst_buf, len,=0A= + if (qcrypto_cipher_encrypt(cipher, src_buf, dst_buf, buf_len,=0A= &local_err) < 0) {=0A= qemu_log_mask(LOG_GUEST_ERROR, "%s: encrypt failed: %s\n",=0A= __func__, error_get_pretty(local_err));=0A= @@ -757,7 +784,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd)=0A= return;=0A= }=0A= } else {=0A= - if (qcrypto_cipher_decrypt(cipher, src_buf, dst_buf, len,=0A= + if (qcrypto_cipher_decrypt(cipher, src_buf, dst_buf, buf_len,=0A= &local_err) < 0) {=0A= qemu_log_mask(LOG_GUEST_ERROR, "%s: decrypt failed: %s\n",=0A= __func__, error_get_pretty(local_err));=0A= @@ -790,13 +817,26 @@ static void do_crypt_operation(AspeedHACEState *s, ui= nt32_t cmd)=0A= * output when encrypting, or of the input when decrypting. Write = it=0A= * back as the IV for the next request.=0A= */=0A= - next_iv =3D (encrypt ? dst_buf : src_buf) + len - blocklen;=0A= + next_iv =3D (encrypt ? dst_buf : src_buf) + buf_len - blocklen;=0A= if (address_space_write(&s->dram_as, ctx_addr + iv_offset,=0A= MEMTXATTRS_UNSPECIFIED, next_iv, blocklen)= ) {=0A= qemu_log_mask(LOG_GUEST_ERROR,=0A= "%s: Failed to write IV, addr=3D0x%" HWADDR_PRIx= "\n",=0A= __func__, ctx_addr + iv_offset);=0A= }=0A= + } else if (mode =3D=3D QCRYPTO_CIPHER_MODE_CTR) {=0A= + /*=0A= + * CTR chains on the counter, which advances by one per block. Add= the=0A= + * number of blocks processed (buf_len / blocklen) and write it ba= ck.=0A= + */=0A= + crypt_be_add(ctx + iv_offset, blocklen, buf_len / blocklen);=0A= + if (address_space_write(&s->dram_as, ctx_addr + iv_offset,=0A= + MEMTXATTRS_UNSPECIFIED, ctx + iv_offset,= =0A= + blocklen)) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: Failed to write IV, addr=3D0x%" HWADDR_PRIx= "\n",=0A= + __func__, ctx_addr + iv_offset);=0A= + }=0A= }=0A= }=0A= =0A= -- =0A= 2.43.0=0A=