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From: Guixin Liu <kanie@linux.alibaba.com>
To: Davidlohr Bueso <dave@stgolabs.net>,
	Jonathan Cameron <jic23@kernel.org>,
	Dave Jiang <dave.jiang@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Dan Williams <djbw@kernel.org>, Ira Weiny <iweiny@kernel.org>,
	Li Ming <ming.li@zohomail.com>, Robert Richter <rrichter@amd.com>
Cc: linux-cxl@vger.kernel.org, xlpang@linux.alibaba.com,
	oliver.yang@linux.alibaba.com
Subject: [PATCH 6/8] cxl/cdat: Fix uninitialized stack use in endpoint bandwidth gathering
Date: Tue, 11 Aug 2026 19:36:06 +0800	[thread overview]
Message-ID: <20260811113608.2815625-7-kanie@linux.alibaba.com> (raw)
In-Reply-To: <20260811113608.2815625-1-kanie@linux.alibaba.com>

cxl_endpoint_gather_bandwidth() combines the endpoint's upstream link
bandwidth with the bandwidth from the endpoint CDAT into an uninitialized
on-stack array:

	struct access_coordinate ep_coord[ACCESS_COORDINATE_MAX];
	...
	cxl_coordinates_combine(ep_coord, pci_coord, perf->cdat_coord);

__cxl_coordinates_combine() only assigns the output bandwidth when both
inputs are non-zero:

	if (c1->write_bandwidth && c2->write_bandwidth)
		out->write_bandwidth = min(...);

That form is intended for the chained 'out == c1' calls that follow, but on
this first call @out is fresh stack. A device whose CDAT DSLBIS does not
report a bandwidth for an access class leaves the corresponding ep_coord
entry untouched, and cxl_bandwidth_add() then accumulates that stack
residue into the region coordinates that are published through the region's
sysfs access coordinate attributes.

pci_coord and sw_coord are less severe but still wrong. Their producers,
cxl_pci_get_bandwidth() and cxl_port_get_switch_dport_bandwidth(), only
fill in the read/write bandwidth fields, so the latency terms are read
uninitialized by the unconditional read_latency and write_latency sums in
the same helper. cxl_bandwidth_add() propagates only bandwidth, so those
sums are discarded rather than published, but the reads themselves are
still undefined behaviour.

Zero initialize all three, which also makes an unreported bandwidth read
back as 0, the value the rest of the CXL performance code already uses to
mean "unknown".

Fixes: a5ab0de0ebaa ("cxl: Calculate region bandwidth of targets with shared upstream link")
Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>
---
 drivers/cxl/core/cdat.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
index 5c9f07262513..3c6a1537f89b 100644
--- a/drivers/cxl/core/cdat.c
+++ b/drivers/cxl/core/cdat.c
@@ -633,9 +633,9 @@ static int cxl_endpoint_gather_bandwidth(struct cxl_region *cxlr,
 	struct cxl_port *endpoint = to_cxl_port(cxled->cxld.dev.parent);
 	struct cxl_port *parent_port = to_cxl_port(endpoint->dev.parent);
 	struct cxl_port *gp_port = to_cxl_port(parent_port->dev.parent);
-	struct access_coordinate pci_coord[ACCESS_COORDINATE_MAX];
-	struct access_coordinate sw_coord[ACCESS_COORDINATE_MAX];
-	struct access_coordinate ep_coord[ACCESS_COORDINATE_MAX];
+	struct access_coordinate pci_coord[ACCESS_COORDINATE_MAX] = { };
+	struct access_coordinate sw_coord[ACCESS_COORDINATE_MAX] = { };
+	struct access_coordinate ep_coord[ACCESS_COORDINATE_MAX] = { };
 	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
 	struct cxl_dev_state *cxlds = cxlmd->cxlds;
 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
-- 
2.43.7


  parent reply	other threads:[~2026-08-11 11:36 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-11 11:36 [PATCH 0/8] cxl: Assorted fixes Guixin Liu
2026-08-11 11:36 ` [PATCH 1/8] cxl/features: Validate the fwctl RPC input length Guixin Liu
2026-08-11 11:36 ` [PATCH 2/8] cxl/features: Bound the Get Feature output by the user output buffer Guixin Liu
2026-08-11 11:36 ` [PATCH 3/8] cxl/core: Fix dport use-after-free via the einj_inject debugfs file Guixin Liu
2026-08-11 16:03   ` Li Ming
2026-08-12  1:58     ` Guixin Liu
2026-08-11 11:36 ` [PATCH 4/8] cxl/pci: Fix NULL pointer dereference in reset detection Guixin Liu
2026-08-11 11:36 ` [PATCH 5/8] cxl/hdm: Fix out of bounds read of the decoder target list Guixin Liu
2026-08-11 11:36 ` Guixin Liu [this message]
2026-08-11 11:36 ` [PATCH 7/8] cxl/mce: Validate the memdev and endpoint before use Guixin Liu
2026-08-11 11:36 ` [PATCH 8/8] cxl/region: Unregister the pmem region bridge on setup failure Guixin Liu
2026-08-11 19:57 ` [PATCH 0/8] cxl: Assorted fixes Alison Schofield
2026-08-12  2:10   ` Guixin Liu
2026-08-12  6:29     ` Richard Cheng
2026-08-12  6:37       ` Guixin Liu

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