From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CD1AC5CFE7 for ; Tue, 11 Aug 2026 12:40:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57A5710EB90; Tue, 11 Aug 2026 12:40:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bKLWpUTd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97F8C10EB90 for ; Tue, 11 Aug 2026 12:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1786452039; x=1817988039; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RbWh2wKrRIrRA+DOE4wuQX3UMBrye5InTonZcRezolU=; b=bKLWpUTdd4WHSjTPA3/+XQ+lj61ZuWyyvZVkM08slES74cX310Q3sqYc 8qdXyHmaZtbCUDChaCETOYc9EQObDVTMF+a6ZGrecFgfnGhZatCM5FIrh TvztblaF6VPz/KlUubq+pO1LJyMmHNvzzpQQw87dYhaDhCA5M77DHOUCS Qy7+mEt2JB0m+uWogAj/qFX/C4U4KtT1Pn61UNB/ZUSku5W2uc5YNRbre eTX2FFXCJ0QPXhjXKkOQFWYYq37j9c/VXSf4tZcXTO9Y5GPvL3E6305R0 hhauBsi+yhhxRe1u0KWYfik+Z6uNQBDA6mePHk6FdtTUWTlZrM5rUWkIn w==; X-CSE-ConnectionGUID: eRM5VG8QTg2D31iP5YLisw== X-CSE-MsgGUID: WRxdrqcqQvWkmZnu0/q4LA== X-IronPort-AV: E=McAfee;i="6800,10657,11871"; a="86912993" X-IronPort-AV: E=Sophos;i="6.25,217,1779174000"; d="scan'208";a="86912993" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2026 05:40:39 -0700 X-CSE-ConnectionGUID: Cwdhs34CTIGXGiZNWCyqpQ== X-CSE-MsgGUID: fGSsrN3YQfK6ulY08A9SXw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,217,1779174000"; d="scan'208";a="265329865" Received: from tejasupa-desk.iind.intel.com (HELO tejasupa-desk) ([10.190.239.37]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2026 05:40:37 -0700 From: Tejas Upadhyay To: intel-xe@lists.freedesktop.org Cc: himal.prasad.ghimiray@intel.com, Tejas Upadhyay Subject: [PATCH V15 03/14] drm/xe: Link LRC BO and its execution Queue Date: Tue, 11 Aug 2026 18:10:07 +0530 Message-ID: <20260811124016.3614699-19-tejas.upadhyay@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260811124016.3614699-16-tejas.upadhyay@intel.com> References: <20260811124016.3614699-16-tejas.upadhyay@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" To establish a link between an LRC BO (Logical Ring Context Buffer Object) and its corresponding execution Queue in the drm/xe driver, you need to store a back-pointer to the queue within the BO's private data structure. This allows the driver to identify and take corrective action on the specific queue if the LRC BO encounters an error (e.g., memory corruption or eviction issues). V3(Sashiko): - Placeholder of 8 byte for non-lrc bo is acceptable - Assign bo-q is safe just use READ_ONCE/WRITE_ONCE V2(MattB): - Handle multiqueue Reviewed-by: Himal Prasad Ghimiray Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/xe/xe_bo_types.h | 3 +++ drivers/gpu/drm/xe/xe_exec_queue.c | 6 ++++++ drivers/gpu/drm/xe/xe_lrc.c | 1 + 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h index e45f24301050..a9c48e440669 100644 --- a/drivers/gpu/drm/xe/xe_bo_types.h +++ b/drivers/gpu/drm/xe/xe_bo_types.h @@ -20,6 +20,7 @@ struct xe_device; struct xe_mem_pool_node; struct xe_vm; +struct xe_exec_queue; #define XE_BO_MAX_PLACEMENTS 3 @@ -42,6 +43,8 @@ struct xe_bo { u32 flags; /** @vm: VM this BO is attached to, for extobj this will be NULL */ struct xe_vm *vm; + /** @q: Queue this BO is attached to, mostly for LRC BO, NULL otherwise */ + struct xe_exec_queue *q; /** @tile: Tile this BO is attached to (kernel BO only) */ struct xe_tile *tile; /** @placements: valid placements for this BO */ diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c index 9f3d022a1463..d6c7f346f49b 100644 --- a/drivers/gpu/drm/xe/xe_exec_queue.c +++ b/drivers/gpu/drm/xe/xe_exec_queue.c @@ -390,6 +390,12 @@ static int __xe_exec_queue_init(struct xe_exec_queue *q, u32 exec_queue_flags) goto err_lrc; } + /* + * The queue ref counts the LRCs, thus it safe for the LRC BO to hold a + * pointer to queue without reference. The reader holds dma_resv ( + * xe_bo_lock) which serializes with xe_lrc_finish(). + */ + WRITE_ONCE(lrc->bo->q, xe_exec_queue_multi_queue_primary(q)); xe_exec_queue_set_lrc(q, lrc, i); if (__lrc) diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 35b4e8289b5f..675902753735 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -1066,6 +1066,7 @@ static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm) static void xe_lrc_finish(struct xe_lrc *lrc) { xe_hw_fence_ctx_finish(&lrc->fence_ctx); + WRITE_ONCE(lrc->bo->q, NULL); xe_bo_unpin_map_no_vm(lrc->bo); xe_bo_unpin_map_no_vm(lrc->seqno_bo); } -- 2.52.0