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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uL5twoODR7h7tXvISrc2qyc1Omt/iP2tMqUXiS6AdPI=; b=BcgWIkaItx4W380piZwuVhTnJnNbQsGRamc5CHvuWRFeSozWUlKVQFamLgsvQ9jJtAqtb4tqnqbPw0vGCB9qZx0VcprAF3MLXgvWnFtyxzSiUNhkTWpsn36FF3+1s3+5GQhCE3dCcRBOJy3rP4TLY/RL8LAEpzvMWq5wUYrHaco= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/2] xen/arm: drop unreachable EL0 check when emulating ACTLR Date: Tue, 11 Aug 2026 15:08:17 +0200 Message-ID: <20260811130818.123862-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811130818.123862-1-michal.orzel@amd.com> References: <20260811130818.123862-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE19:EE_|CY8PR12MB8216:EE_ X-MS-Office365-Filtering-Correlation-Id: 48d65d3f-6abd-4c34-73a3-08def7a99fe4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700016|23010399003|22082099003|18002099003|11063799006|56012099006|3023799007|6133799003|10067099003; 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ACTLR) originates from EL0. That branch cannot be taken. ACTLR_EL1 can be accessed by EL1 and above, and no enable makes them accessible at EL0. The only trap covering them, HCR_EL2.TACR (HCR.TAC on AArch32), applies to accesses from EL1 only. Refer Arm ARM (DDI 0487M.b) D1.4.5.6 "Prioritization of Synchronous exceptions": "attempting to execute an instruction that is defined to never be accessible at the current Exception level and Security state, regardless of any enables or traps" is priority 18, whereas an exception taken to EL2 as the result of a configuration control in HCR_EL2 is priority 24. The former wins, so an access from EL0 is UNDEFINED and the TACR trap is not taken. An EL0 access therefore never reaches EL2: it is taken to EL1, as Xen never sets HCR_EL2.TGE for guests, and it is reported with EC=0x00 (Unknown reason) rather than EC=0x18/0x03. Signed-off-by: Michal Orzel --- xen/arch/arm/arm64/vsysreg.c | 2 -- xen/arch/arm/vcpreg.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index a02ad951f9c1..a59848889659 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -95,8 +95,6 @@ void do_sysreg(struct cpu_user_regs *regs, * ARMv8 (DDI 0487A.d): D7.2.1 */ case HSR_SYSREG_ACTLR_EL1: - if ( regs_mode_is_user(regs) ) - return inject_undef_exception(regs); if ( hsr.sysreg.read ) set_user_reg(regs, regidx, v->arch.actlr); break; diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index d6f9326b712c..749ce6d3a57c 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -219,8 +219,6 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) * ARMv8 (DDI 0487A.d): G6.2.1 */ case HSR_CPREG32(ACTLR): - if ( regs_mode_is_user(regs) ) - return inject_undef_exception(regs); if ( cp32.read ) set_user_reg(regs, regidx, v->arch.actlr); break; -- 2.43.0