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From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Emmanuel Blot" <emmanuel.blot@free.fr>,
	"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 31/83] tests/qtest: adc128d818: test operating modes and power control
Date: Tue, 11 Aug 2026 18:28:46 +0200	[thread overview]
Message-ID: <20260811162938.1403216-32-clg@redhat.com> (raw)
In-Reply-To: <20260811162938.1403216-1-clg@redhat.com>

From: Emmanuel Blot <emmanuel.blot@free.fr>

Cover advanced-configuration mode selection (single-ended,
pseudo-differential pairs, and mixed) and the reset of readings on
reconfiguration, plus channel disable, one-shot conversion, deep
shutdown, BUSY_STATUS lifecycle, and conversion-rate gating.

Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
Link: https://lore.kernel.org/qemu-devel/20260707091609.97759-6-emmanuel.blot@free.fr
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/adc128d818-test.c | 377 ++++++++++++++++++++++++++++++++++
 1 file changed, 377 insertions(+)

diff --git a/tests/qtest/adc128d818-test.c b/tests/qtest/adc128d818-test.c
index 3e3fabb8d9f1..91eda5ca74d0 100644
--- a/tests/qtest/adc128d818-test.c
+++ b/tests/qtest/adc128d818-test.c
@@ -447,6 +447,368 @@ static void test_temp_hysteresis(void *obj, void *data,
     g_assert_cmphex(status & 0x80u, ==, 0x00);
 }
 
+/* Channel disable prevents conversion */
+static void test_channel_disable(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_CH_DISABLE, 0x01);
+    g_test_message("Disabled channel 0");
+
+    qmp_adc128d818_set("ain0", 1280);
+    g_test_message("Injected ain0 = 1280 mV (disabled)");
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Read ch0 (disabled): raw 0x%04x", reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    qmp_adc128d818_set("ain1", 1280);
+    g_test_message("Injected ain1 = 1280 mV (enabled)");
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 1u);
+    g_test_message("Read ch1 (enabled): raw 0x%04x -> %u mV", reading,
+             (reading >> 4u) * INTERNAL_VREF_MV / 4096u);
+    g_assert_cmphex(reading, ==, 0x8000);
+}
+
+/* One-shot conversion in shutdown mode */
+static void test_one_shot(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    qmp_adc128d818_set("ain0", 1280);
+    g_test_message("Injected ain0 = 1280 mV (device stopped)");
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Read ch0 before one-shot: raw 0x%04x", reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    g_assert_cmphex(i2c_get8(dev, REG_ONE_SHOT), ==, 0x00);
+
+    i2c_set8(dev, REG_ONE_SHOT, 0x00);
+    g_test_message("Triggered one-shot conversion with value 0x00");
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Read ch0 after one-shot: raw 0x%04x -> %u mV", reading,
+             (reading >> 4u) * INTERNAL_VREF_MV / 4096u);
+    g_assert_cmphex(reading, ==, 0x8000);
+}
+
+/* Mode 1 makes channel 7 a voltage input instead of temperature */
+static void test_mode_selection(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_1);
+    g_test_message("Set mode 1 (all voltage channels)");
+
+    qmp_adc128d818_set("ain7", 1280);
+    qmp_adc128d818_set("temperature", 50000);
+    g_test_message("Injected ain7 = 1280 mV, temperature = 50000 mC");
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 7u);
+    g_test_message("Read ch7 (mode 1): raw 0x%04x -> %u mV", reading,
+             (reading >> 4u) * INTERNAL_VREF_MV / 4096u);
+    g_assert_cmphex(reading, ==, 0x8000);
+}
+
+/* Mode 2 - 4 pseudo-differential pairs */
+static void test_mode2_diff(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_2);
+    g_test_message("Set mode 2 (4 pseudo-differential pairs)");
+
+    qmp_adc128d818_set("ain0", 2000);
+    qmp_adc128d818_set("ain1", 720);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Pair 0 (IN0-IN1): raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    qmp_adc128d818_set("ain3", 1920);
+    qmp_adc128d818_set("ain2", 640);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 1u);
+    g_test_message("Pair 1 (IN3-IN2): raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    qmp_adc128d818_set("ain4", 1500);
+    qmp_adc128d818_set("ain5", 220);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 2u);
+    g_test_message("Pair 2 (IN4-IN5): raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    qmp_adc128d818_set("ain7", 2560);
+    qmp_adc128d818_set("ain6", 1280);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 3u);
+    g_test_message("Pair 3 (IN7-IN6): raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 4u);
+    g_test_message("Reserved ch4: raw 0x%04x (expect 0x0000)", reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    qmp_adc128d818_set("ain0", 500);
+    qmp_adc128d818_set("ain1", 1000);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Pair 0 negative dV: raw 0x%04x (expect 0x0000)", reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+}
+
+/* Mode 3 - 4 single-ended + 2 pseudo-differential pairs */
+static void test_mode3_mixed(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_3);
+    g_test_message("Set mode 3 (4 single-ended + 2 differential)");
+
+    qmp_adc128d818_set("ain0", 1280);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Ch0 single-ended: raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    qmp_adc128d818_set("ain4", 1500);
+    qmp_adc128d818_set("ain5", 220);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 4u);
+    g_test_message("Ch4 diff (IN4-IN5): raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    qmp_adc128d818_set("ain7", 2560);
+    qmp_adc128d818_set("ain6", 1280);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 5u);
+    g_test_message("Ch5 diff (IN7-IN6): raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 6u);
+    g_test_message("Reserved ch6: raw 0x%04x (expect 0x0000)", reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    qmp_adc128d818_set("temperature", 25000);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 7u);
+    g_test_message("Ch7 temperature: raw 0x%04x (expect 0x1900)", reading);
+    g_assert_cmphex(reading, ==, 0x1900);
+}
+
+/* Mode change resets channel readings and interrupt status */
+static void test_mode_change_reset(void *obj, void *data,
+                                   QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+    uint8_t status;
+
+    qmp_adc128d818_set("ain0", 1280);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Before mode change, ch0: raw 0x%04x", reading);
+    g_assert_cmphex(reading, !=, 0x0000);
+
+    i2c_set8(dev, REG_CONFIG, 0x00);
+    i2c_set8(dev, REG_LIMIT_BASE, 0x10);
+    qmp_adc128d818_set("ain0", 2560);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    i2c_set8(dev, REG_CONFIG, 0x00);
+    i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_2);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After mode change, ch0: raw 0x%04x (expect 0x0000)",
+                   reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    status = i2c_get8(dev, REG_INT_STATUS);
+    g_test_message("After mode change, INT_STATUS: 0x%02x (expect 0x00)",
+                   status);
+    g_assert_cmphex(status, ==, 0x00);
+
+    g_assert_cmphex(i2c_get8(dev, REG_LIMIT_BASE), ==, 0x10);
+    g_test_message("Limit register preserved after mode change");
+}
+
+/* QOM property changes trigger correct differential conversion */
+static void test_diff_qom_trigger(void *obj, void *data,
+                                  QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION);
+    i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_2);
+
+    qmp_adc128d818_set("ain0", 0);
+    qmp_adc128d818_set("ain1", 0);
+    qmp_adc128d818_set("ain2", 0);
+    qmp_adc128d818_set("ain3", 0);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    qmp_adc128d818_set("ain0", 2000);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After ain0=2000, ain1=0: pair0 = 0x%04x (expect 0xC800)",
+             reading);
+    g_assert_cmphex(reading, ==, 0xC800);
+
+    qmp_adc128d818_set("ain1", 720);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After ain1=720: pair0 = 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    qmp_adc128d818_set("ain3", 1920);
+    qmp_adc128d818_set("ain2", 640);
+    reading = i2c_get16(dev, REG_CH_READING_BASE + 1u);
+    g_test_message("Pair 1 (IN3-IN2) via QOM: 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+}
+
+/* One-shot conversion works in deep shutdown */
+static void test_deep_shutdown(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION);
+
+    qmp_adc128d818_set("ain0", 1280);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    i2c_set8(dev, REG_DEEP_SHUTDOWN, 0x01);
+    g_test_message("DEEP_SHUTDOWN write while running rejected");
+    g_assert_cmphex(i2c_get8(dev, REG_DEEP_SHUTDOWN), ==, 0x00);
+
+    i2c_set8(dev, REG_CONFIG, 0x00);
+    i2c_set8(dev, REG_DEEP_SHUTDOWN, 0x01);
+    qmp_adc128d818_set("ain0", 0);
+
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Deep shutdown, no one-shot: raw 0x%04x (expect 0x8000)",
+                   reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+
+    i2c_set8(dev, REG_ONE_SHOT, 0x01);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("Deep shutdown one-shot: raw 0x%04x (expect 0x0000)",
+                   reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    g_assert_cmphex(i2c_get8(dev, REG_DEEP_SHUTDOWN), ==, 0x01);
+
+    i2c_set8(dev, REG_DEEP_SHUTDOWN, 0x00);
+    qmp_adc128d818_set("ain0", 1280);
+    i2c_set8(dev, REG_ONE_SHOT, 0x01);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After exit shutdown: raw 0x%04x (expect 0x8000)", reading);
+    g_assert_cmphex(reading, ==, 0x8000);
+}
+
+/* BUSY_STATUS NOT_READY clears after first conversion */
+static void test_busy_status(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION);
+
+    g_assert_cmphex(i2c_get8(dev, REG_BUSY_STATUS) & 0x02, ==, 0x02);
+    g_test_message("After reset: BUSY_STATUS = 0x%02x (NOT_READY set)",
+             i2c_get8(dev, REG_BUSY_STATUS));
+
+    qmp_adc128d818_set("ain0", 0);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+
+    g_assert_cmphex(i2c_get8(dev, REG_BUSY_STATUS) & 0x02, ==, 0x00);
+    g_test_message("After conversion: BUSY_STATUS = 0x%02x (NOT_READY cleared)",
+             i2c_get8(dev, REG_BUSY_STATUS));
+}
+
+/* Programming Channel Disable resets channel readings */
+static void test_chan_disable_clears(void *obj, void *data,
+                                     QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION);
+
+    qmp_adc128d818_set("ain0", 1280);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+    g_assert_cmphex(i2c_get16(dev, REG_CH_READING_BASE), ==, 0x8000);
+
+    i2c_set8(dev, REG_CONFIG, 0x00);
+    i2c_set8(dev, REG_CH_DISABLE, 0x02);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After CH_DISABLE write: ch0 raw 0x%04x (expect 0x0000)",
+                   reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+}
+
+/* Programming Advanced Configuration always resets channel readings */
+static void test_adv_config_clears(void *obj, void *data,
+                                   QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+    uint16_t reading;
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION);
+
+    qmp_adc128d818_set("ain0", 1280);
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+    g_assert_cmphex(i2c_get16(dev, REG_CH_READING_BASE), ==, 0x8000);
+
+    i2c_set8(dev, REG_CONFIG, 0x00);
+    i2c_set8(dev, REG_ADV_CONFIG, 0x00);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After same-mode ADV_CONFIG: ch0 0x%04x (expect 0x0000)",
+                   reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+    g_assert_cmphex(i2c_get16(dev, REG_CH_READING_BASE), ==, 0x8000);
+    i2c_set8(dev, REG_CONFIG, 0x00);
+    qmp_adc128d818_set("ext-vref-mv", 4096);
+    i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_EXT_REF_EN);
+    reading = i2c_get16(dev, REG_CH_READING_BASE);
+    g_test_message("After ext-vref toggle: ch0 0x%04x (expect 0x0000)",
+                   reading);
+    g_assert_cmphex(reading, ==, 0x0000);
+}
+
+/* Conversion Rate register may only be programmed while in shutdown */
+static void test_conv_rate(void *obj, void *data, QGuestAllocator *alloc)
+{
+    QI2CDevice *dev = (QI2CDevice *)obj;
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION);
+
+    i2c_set8(dev, REG_CONV_RATE, 0x01);
+    g_assert_cmphex(i2c_get8(dev, REG_CONV_RATE), ==, 0x01);
+
+    i2c_set8(dev, REG_CONFIG, CONFIG_START);
+    i2c_set8(dev, REG_CONV_RATE, 0x00);
+    g_test_message("CONV_RATE while running: 0x%02x (expect unchanged 0x01)",
+             i2c_get8(dev, REG_CONV_RATE));
+    g_assert_cmphex(i2c_get8(dev, REG_CONV_RATE), ==, 0x01);
+}
+
 static void adc128d818_register_nodes(void)
 {
     QOSGraphEdgeOptions opts = {
@@ -475,5 +837,20 @@ static void adc128d818_register_nodes(void)
     qos_add_test("int-clear", "adc128d818", test_int_clear, NULL);
     qos_add_test("low-limit", "adc128d818", test_low_limit, NULL);
     qos_add_test("temp-hysteresis", "adc128d818", test_temp_hysteresis, NULL);
+    qos_add_test("channel-disable", "adc128d818", test_channel_disable, NULL);
+    qos_add_test("one-shot", "adc128d818", test_one_shot, NULL);
+    qos_add_test("mode-selection", "adc128d818", test_mode_selection, NULL);
+    qos_add_test("mode2-diff", "adc128d818", test_mode2_diff, NULL);
+    qos_add_test("mode3-mixed", "adc128d818", test_mode3_mixed, NULL);
+    qos_add_test("mode-change-reset", "adc128d818", test_mode_change_reset,
+                 NULL);
+    qos_add_test("diff-qom-trigger", "adc128d818", test_diff_qom_trigger, NULL);
+    qos_add_test("deep-shutdown", "adc128d818", test_deep_shutdown, NULL);
+    qos_add_test("busy-status", "adc128d818", test_busy_status, NULL);
+    qos_add_test("chan-disable-clears", "adc128d818", test_chan_disable_clears,
+                 NULL);
+    qos_add_test("adv-config-clears", "adc128d818", test_adv_config_clears,
+                 NULL);
+    qos_add_test("conv-rate", "adc128d818", test_conv_rate, NULL);
 }
 libqos_init(adc128d818_register_nodes);
-- 
2.55.0



  parent reply	other threads:[~2026-08-11 16:36 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-11 16:28 [PULL 00/83] aspeed queue Cédric Le Goater
2026-08-11 16:28 ` [PULL 01/83] hw/arm/aspeed: Add missing PCI_EXPRESS -> PCIE_PORT Kconfig dependency Cédric Le Goater
2026-08-11 16:28 ` [PULL 02/83] hw/arm/aspeed: Add missing Kconfig dependencies on required components Cédric Le Goater
2026-08-11 16:28 ` [PULL 03/83] hw/arm/aspeed: Add missing Kconfig dependencies on optional components Cédric Le Goater
2026-08-11 16:28 ` [PULL 04/83] hw/usb/hcd-ehci: Change descriptor addresses to 64-bit with migration compatibility Cédric Le Goater
2026-08-11 16:28 ` [PULL 05/83] hw/usb/hcd-ehci: Add property to advertise 64-bit addressing capability Cédric Le Goater
2026-08-11 16:28 ` [PULL 06/83] hw/usb/hcd-ehci: Implement 64-bit QH descriptor addressing Cédric Le Goater
2026-08-11 16:28 ` [PULL 07/83] hw/usb/hcd-ehci: Implement 64-bit qTD " Cédric Le Goater
2026-08-11 16:28 ` [PULL 08/83] hw/usb/hcd-ehci: Implement 64-bit iTD " Cédric Le Goater
2026-08-11 16:28 ` [PULL 09/83] hw/usb/hcd-ehci: Implement 64-bit siTD " Cédric Le Goater
2026-08-11 16:28 ` [PULL 10/83] hw/usb/hcd-ehci: Add ctrldssegment-default property Cédric Le Goater
2026-08-11 16:28 ` [PULL 11/83] hw/arm/aspeed_ast27x0: Set EHCI ctrldssegment-default Cédric Le Goater
2026-08-11 16:28 ` [PULL 12/83] hw/arm/aspeed_ast27x0: Enable 64-bit EHCI DMA addressing Cédric Le Goater
2026-08-11 16:28 ` [PULL 13/83] tests/functional/aarch64/test_aspeed_ast2700: Add USB EHCI test for AST2700 A1/A2 Cédric Le Goater
2026-08-11 16:28 ` [PULL 14/83] tests/qtest: aspeed_smc: Introduce read_page_mem_fn for page read helpers Cédric Le Goater
2026-08-11 16:28 ` [PULL 15/83] tests/qtest: aspeed_smc: Add fast-read test coverage Cédric Le Goater
2026-08-11 16:28 ` [PULL 16/83] tests/qtest: aspeed_smc: Add Dual Output Read (DOR) " Cédric Le Goater
2026-08-11 16:28 ` [PULL 17/83] tests/qtest: aspeed_smc: Add Quad Output Read (QOR) " Cédric Le Goater
2026-08-11 16:28 ` [PULL 18/83] hw/misc/aspeed_scu: Introduce Aspeed2700SCUState Cédric Le Goater
2026-08-11 16:28 ` [PULL 19/83] hw/arm/aspeed: Use Aspeed2700SCUState for AST2700 users Cédric Le Goater
2026-08-11 16:28 ` [PULL 20/83] hw/arm/aspeed_ast27x0: Move SCU link into AST27x0 coprocessors Cédric Le Goater
2026-08-11 16:28 ` [PULL 21/83] hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO Cédric Le Goater
2026-08-11 16:28 ` [PULL 22/83] hw/arm/aspeed_ast27x0: Pass realized PSP SoC to SSP/TSP initialization Cédric Le Goater
2026-08-11 16:28 ` [PULL 23/83] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP Cédric Le Goater
2026-08-11 16:28 ` [PULL 24/83] hw/arm/ast27x0: Share FMC controller with SSP " Cédric Le Goater
2026-08-11 16:28 ` [PULL 25/83] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for AST2700 Cédric Le Goater
2026-08-11 16:28 ` [PULL 26/83] tests/qtest/ast2700-smc-test: Add Data FIFO mode test Cédric Le Goater
2026-08-11 16:28 ` [PULL 27/83] hw/sensor: adc128d818: add 12-bit 8-channel ADC device Cédric Le Goater
2026-08-11 16:28 ` [PULL 28/83] tests/qtest: adc128d818: add test harness and register access Cédric Le Goater
2026-08-11 16:28 ` [PULL 29/83] tests/qtest: adc128d818: test voltage and temperature conversion Cédric Le Goater
2026-08-11 16:28 ` [PULL 30/83] tests/qtest: adc128d818: test limit interrupts Cédric Le Goater
2026-08-11 16:28 ` Cédric Le Goater [this message]
2026-08-11 16:28 ` [PULL 32/83] hw/arm/aspeed: anacapa: use ASCII in comments Cédric Le Goater
2026-08-11 16:28 ` [PULL 33/83] hw/arm: anacapa: add ADC128D818 devices Cédric Le Goater
2026-08-11 16:28 ` [PULL 34/83] hw/gpio: pca9552: register types with DEFINE_TYPES() Cédric Le Goater
2026-08-11 16:28 ` [PULL 35/83] hw/gpio: pca9552: move PCA955xState definition out of the header Cédric Le Goater
2026-08-11 16:28 ` [PULL 36/83] hw/gpio: pca9552: rename I2CSlave member to parent_obj Cédric Le Goater
2026-08-11 16:28 ` [PULL 37/83] hw/gpio: pca9552: default description to the instantiated type name Cédric Le Goater
2026-08-11 16:28 ` [PULL 38/83] hw/gpio: pca9552: declare pca9555 device as an alias of pca9535 device Cédric Le Goater
2026-08-11 16:28 ` [PULL 39/83] hw/gpio: pca9552: use the Resettable interface instead of legacy reset Cédric Le Goater
2026-08-11 16:28 ` [PULL 40/83] hw/gpio: pca9552: apply input polarity inversion on read Cédric Le Goater
2026-08-11 16:28 ` [PULL 41/83] hw/gpio: pca9552: conform GPIO command handling to the datasheet Cédric Le Goater
2026-08-11 16:28 ` [PULL 42/83] hw/gpio: pca9552: expose GPIO pins as pin%d QOM properties Cédric Le Goater
2026-08-11 16:28 ` [PULL 43/83] tests/qtest: add PCA9555 register access tests Cédric Le Goater
2026-08-11 16:28 ` [PULL 44/83] tests/qtest: pca9555: test output-to-input reflection and pull-ups Cédric Le Goater
2026-08-11 16:29 ` [PULL 45/83] tests/qtest: pca9555: test polarity inversion Cédric Le Goater
2026-08-11 16:29 ` [PULL 46/83] tests/qtest: pca9555: test auto-increment and command wrapping Cédric Le Goater
2026-08-11 16:29 ` [PULL 47/83] tests/qtest: pca9552: test behaviour specific to the LED variant Cédric Le Goater
2026-08-11 16:29 ` [PULL 48/83] hw/gpio: pca9554: add PCA9536 support Cédric Le Goater
2026-08-11 16:29 ` [PULL 49/83] hw/gpio: pca9554: add hw-dir property honoring the configured pin direction Cédric Le Goater
2026-08-11 16:29 ` [PULL 50/83] hw/gpio: pca9554: reflect push-pull outputs in the input register Cédric Le Goater
2026-08-11 16:29 ` [PULL 51/83] hw/gpio: pca9554: expose pin%d as a string property Cédric Le Goater
2026-08-11 16:29 ` [PULL 52/83] tests/qtest: add PCA9554 register access tests Cédric Le Goater
2026-08-11 16:29 ` [PULL 53/83] tests/qtest: pca9554: test output-to-input reflection and pull-ups Cédric Le Goater
2026-08-11 16:29 ` [PULL 54/83] tests/qtest: pca9554: test polarity inversion Cédric Le Goater
2026-08-11 16:29 ` [PULL 55/83] tests/qtest: pca9554: test absence of command auto-increment Cédric Le Goater
2026-08-11 16:29 ` [PULL 56/83] tests/qtest: pca9554: test the PCA9536 4-bit variant Cédric Le Goater
2026-08-11 16:29 ` [PULL 57/83] hw/arm: catalina: model PCA9555 IO expanders with their own type Cédric Le Goater
2026-08-11 16:29 ` [PULL 58/83] hw/arm: catalina: add NIC and FIO temperature sensors Cédric Le Goater
2026-08-11 16:29 ` [PULL 59/83] hw/i2c/aspeed_i2c: Support the AST2700 master buffer mode Cédric Le Goater
2026-08-11 16:29 ` [PULL 60/83] tests/functional/aarch64/test_aspeed_ast2700a2: Update ASPEED SDK v11.03 Cédric Le Goater
2026-08-11 16:29 ` [PULL 61/83] tests/functional/aarch64/test_aspeed_ast2700a1: " Cédric Le Goater
2026-08-11 16:29 ` [PULL 62/83] tests/functional/aarch64/test_aspeed_ast2700fc: " Cédric Le Goater
2026-08-11 16:29 ` [PULL 63/83] tests/functional/arm/test_aspeed_ast2600_sdk: " Cédric Le Goater
2026-08-11 16:29 ` [PULL 64/83] tests/functional/arm/test_aspeed_ast2500_sdk: " Cédric Le Goater
2026-08-11 16:29 ` [PULL 65/83] tests/functional/arm/test_aspeed_ast1030: Update ASPEED Zephyr SDK v03.08 Cédric Le Goater
2026-08-11 16:29 ` [PULL 66/83] tests/functional/arm/test_aspeed_ast1060: Update ASPEED ZEPHYR PROJECT v03.07 Cédric Le Goater
2026-08-11 16:29 ` [PULL 67/83] hw/arm/aspeed: avoid sign mismatch on sscanf for uart property Cédric Le Goater
2026-08-11 16:29 ` [PULL 68/83] hw/misc/aspeed_hace: Support the crypto command in direct access mode Cédric Le Goater
2026-08-11 16:29 ` [PULL 69/83] tests/qtest/aspeed-hace: Test the crypto command on the AST2500 Cédric Le Goater
2026-08-11 16:29 ` [PULL 70/83] hw/misc/aspeed_hace: Support scatter-gather mode for the crypto command Cédric Le Goater
2026-08-11 16:29 ` [PULL 71/83] hw/misc/aspeed_hace: Support the CTR " Cédric Le Goater
2026-08-11 16:29 ` [PULL 72/83] tests/qtest/aspeed-hace: Test the crypto command on the AST2600 Cédric Le Goater
2026-08-11 16:29 ` [PULL 73/83] tests/qtest/aspeed-hace: Test the crypto command on the AST1030 Cédric Le Goater
2026-08-11 16:29 ` [PULL 74/83] crypto/cipher: Add GCM to QCryptoCipherMode Cédric Le Goater
2026-08-11 16:29 ` [PULL 75/83] crypto/cipher: Add setaad/gettag for AEAD modes Cédric Le Goater
2026-08-11 16:29 ` [PULL 76/83] crypto/cipher-gcrypt: Implement AES-GCM Cédric Le Goater
2026-08-11 16:29 ` [PULL 77/83] crypto/cipher-nettle: " Cédric Le Goater
2026-08-11 16:29 ` [PULL 78/83] crypto/cipher-gnutls: " Cédric Le Goater
2026-08-11 16:29 ` [PULL 79/83] tests/unit/test-crypto-cipher: Test AES-GCM mode Cédric Le Goater
2026-08-11 16:29 ` [PULL 80/83] hw/misc/aspeed_hace: Support 64-bit DMA for the crypto command Cédric Le Goater
2026-08-11 16:29 ` [PULL 81/83] hw/misc/aspeed_hace: Support the AES-GCM mode " Cédric Le Goater
2026-08-11 16:29 ` [PULL 82/83] hw/misc/aspeed_hace: Enable the crypto command on the AST2700 Cédric Le Goater
2026-08-11 16:29 ` [PULL 83/83] tests/qtest/aspeed-hace: Test " Cédric Le Goater
2026-08-12 16:15 ` [PULL 00/83] aspeed queue Richard Henderson

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