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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5890 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Different from detect_and_reset, reset_hw_queue performs per queue reset by sending reset_queue_only=1 and hung queue's doorbell_offset to MES in RESET packet. enable_compute_pipe_reset=1 also needs to be set in SET_HW_RESOURCES so when queue reset fails, MES will proceed pipe reset. This patch also fix a bug in mes_v12_1_reset_hw_queue function. Instead of using MESAPI__RESET offset for api_status, the existing code uses MESAPI__REMOVE_QUEUE. Signed-off-by: Amber Lin --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index f1098118d5c0..9c01dc97d271 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -388,7 +388,7 @@ static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ - /*mes_reset_queue_pkt.reset_queue_only = 1;*/ + mes_reset_queue_pkt.reset_queue_only = 1; if (mes->adev->enable_uni_mes) pipe = AMDGPU_MES_KIQ_PIPE; @@ -398,7 +398,7 @@ static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, pipe, &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), - offsetof(union MESAPI__REMOVE_QUEUE, api_status)); + offsetof(union MESAPI__RESET, api_status)); } static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, @@ -743,6 +743,8 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; + /* proceeds pipe reset if queue reset fails */ + mes_set_hw_res_pkt.enable_compute_pipe_reset = 1; /* * Keep oversubscribe timer for sdma . When we have unmapped doorbell -- 2.43.0