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[129.27.234.122]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aabab7asm68945585e9.6.2026.08.12.05.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Aug 2026 05:21:19 -0700 (PDT) From: Simon Scherer To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, Simon Scherer Subject: [PATCH] target/i386: Set aliased x87 exponent bits to all 1s for MMX register writes Date: Wed, 12 Aug 2026 14:21:14 +0200 Message-ID: <20260812122114.510447-1-scherer.simon89@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=scherer.simon89@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Per the Intel SDM (Vol 3, 15.2), writing an MMX register also sets bits 64-79 of the aliased x87 register to all 1s. gen_writeback() never does this for X86_OP_MMX destinations, so those bits keep whatever the x87 side left there (e.g. 0 after finit/fldz). A later x87 instruction such as fucomi/fucomip can then read a stale finite value where real hardware guarantees a NaN encoding, changing comparison results and flags. Set the high 16 bits to 0xffff when writing back to a MMX register (not memory). Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4105 Signed-off-by: Simon Scherer --- target/i386/tcg/emit.c.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 473f415766..e2f0b4b1f7 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -352,6 +352,10 @@ static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv } break; case X86_OP_MMX: + if (!op->has_ea) { + tcg_gen_st16_i32(tcg_constant_i32(0xffff), tcg_env, + MMX_OFFSET(op->n) + offsetof(floatx80, high)); + } break; case X86_OP_SSE: if (!op->has_ea && (s->prefix & PREFIX_VEX) && op->ot <= MO_128) { -- 2.53.0