From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50875435EFE; Thu, 13 Aug 2026 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; cv=none; b=QYHgSoP9PocqI3A+NsGYzrFzOwYEGpx2WAwK2xtIgzMOSFy5GPri1NHA4V5De87547zR+LLxtjaQOqBtzHLk4Yp0CgUOpBLXlOkn6wvmDNkb6giFysf5xVX/TrF1FWjfIprccsajLBJd4S6i0JVZMOhvgB+SGrnLv4+gK8fhklA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786622400; c=relaxed/simple; bh=KXlTSNgL7obcfAAu2qQszrvsiNWFTE6hySuQAhmN6t4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rnp90OYiH+0fFp5I0ta4k3cPCdwgsE6AOaXdBmBBCn21pscba8Msr2So3W6uN1/Z+MhyqLZA1wzHpCfDcB4T6sY/kD7GmzTv0xbkXjqEC7X0A/nXWZp7SMvcV/tVkWmnsMtOTZzLBPiFS3NZKX5sDyqNQKYDhB1Ud0YjqhZ/Y/4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EPdSPb45; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EPdSPb45" Received: by smtp.kernel.org (Postfix) with ESMTPS id DE693C2BCF7; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786622399; bh=KXlTSNgL7obcfAAu2qQszrvsiNWFTE6hySuQAhmN6t4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EPdSPb45Zy8CTDw4NvBcMk9XScBXCtbeBc1H/BlGXxrYcicntrrdc0uiqx5Rlhsl7 F0lY9fBWFQ38xRsR98NDrk0A760EQsUzuj0XDir6XGamOhqDwEk8v3YacMcRYOvYRt GdusGcmMr9W/jaFHsiyhlhpkVIuUnNQlJVIy5l5prITmivfEbKRKAhaI5Fe56spiu0 2D78kIKSxsdves4q4soe71CUPs/RLeqCGuSq8+98Wke1oBq+BxOjwj44K24bf4G4Nx j1fiQZem2lp/wINWtK8m4PQihmkq9gISDf4d29IrmgLBu483HNm4XHbgIJ3w8zAgzQ P2J7TEHObbTkA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA5F5C5CFDB; Thu, 13 Aug 2026 11:59:59 +0000 (UTC) From: Colin Huang via B4 Relay Date: Thu, 13 Aug 2026 19:59:33 +0800 Subject: [PATCH v5 03/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-3-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=5864; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=uFd3k24VxEypaHLespXpLRjwFFWss5Y43arELHuz9Hk=; b=TBYlPuvOsM9bDcK0FYWJE2UD2QbC/w1OSMvXwTtlAiQWusFTznZ+jXCZ8UimnevIIFI7o6qBv nps64VLkgymDOnqklpS6+XiU74CVTB+1QXtjOHjUC5D1gP0L0UBPLE/ X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC EVT2 hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 178 +++++++++++++++++++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts new file mode 100644 index 000000000000..4a6ae7c6cbf8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt1.dts" + +/ { + model = "Facebook Anacapa BMC"; + compatible = "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; +}; + +&sgpiom0 { + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 209eef65cedb..1848ca347621 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include "aspeed-bmc-facebook-anacapa-evt1.dts" +#include "aspeed-bmc-facebook-anacapa-evt2.dts" -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Colin Huang Date: Thu, 13 Aug 2026 19:59:33 +0800 Subject: [PATCH v5 03/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260813-anacapa-devlop-phase-devicetree-v5-3-c7058f63dc67@gmail.com> References: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> In-Reply-To: <20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786622378; l=5864; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=uFd3k24VxEypaHLespXpLRjwFFWss5Y43arELHuz9Hk=; b=TBYlPuvOsM9bDcK0FYWJE2UD2QbC/w1OSMvXwTtlAiQWusFTznZ+jXCZ8UimnevIIFI7o6qBv nps64VLkgymDOnqklpS6+XiU74CVTB+1QXtjOHjUC5D1gP0L0UBPLE/ X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 List-Id: B4 Relay Submissions Add a development-phase devicetree for the Facebook Anacapa BMC EVT2 hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 178 +++++++++++++++++++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts new file mode 100644 index 000000000000..4a6ae7c6cbf8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt1.dts" + +/ { + model = "Facebook Anacapa BMC"; + compatible = "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; +}; + +&sgpiom0 { + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 209eef65cedb..1848ca347621 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include "aspeed-bmc-facebook-anacapa-evt1.dts" +#include "aspeed-bmc-facebook-anacapa-evt2.dts" -- 2.34.1