From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 581F024DCF6; Thu, 13 Aug 2026 02:20:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786587620; cv=none; b=rFyFRzU1KUaNnaxWH3UZr0JL+EjDoPaSKuXxJDMzf0ZU8htURolVMNDbNZ2KrPa7QMBBNfVnuiO8kLWxYURiKaAg4z+q8F9aogBEunbZikn7z7vUiwRZ30Kf+ZMwuba1jIIEMzEW9oL29PHBFyKDLD40dIu+3vXqRH+JozqR5+Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786587620; c=relaxed/simple; bh=zH06ZKSgGhEhXr0gPfiGkd8DxI44+kr5wz8zEOUWQZk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fgo7OUMxSEwOo8b5420tSUbi3x2bIwt37Cgb0F4Yu9YYLvXBHsvcJoWRLFjMGHUnNap+cfkZ61LkhA48LrbQv6OBJ77oVEEAF6ZD4shSYCt1zbAQEH1H1UT7TUgHuqesxhtRg3YnSSfeaU0JHe5bHAvB5wtnXpXWbpUU3YHqaiw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b54acgNZ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b54acgNZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E79EC1F00A3E; Thu, 13 Aug 2026 02:20:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786587619; bh=56BaSgitaCOqK+plEdyRoTXW75Ul7dUQbsnofeonq2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=b54acgNZyd8vGhYdRRYpbxz0Zc/bz1/1S1fnQak8e2Nl7ogo5RpUmPtlcBNNFArys K1u/fPN5MXNcEDv72S1QDo34/b8WlNoYXzYIln+qlkx+WBLJlXM+Bujz0iO5v63IcN mFm6W+IrR/O1hZjHj29TU+abXdRAQk+cI6osQVNL2CxFwlpj/lckaQYD6JKkCjJM1V +2a5Ebc6Bc4j4CgR1qO15zFBfsFv/XAtnWOsn3aoJfaR0M5rp2jlaetOUB8Gyn2IMq EVDwe4Uxjr+r/qhY9a4myDhzsaJh/lOwEZVcn7QOjANoQDALnf5S+4HYgnebySY17E TuaxZpBtTB8uA== From: Eric Biggers To: x86@kernel.org Cc: linux-um@lists.infradead.org, linux-raid@vger.kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Christoph Hellwig , Andrew Morton , Eric Biggers Subject: [PATCH v3 1/8] x86/fpu: Check for missing AVX and AVX-512 xstate bits Date: Wed, 12 Aug 2026 19:14:59 -0700 Message-ID: <20260813021506.55129-2-ebiggers@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260813021506.55129-1-ebiggers@kernel.org> References: <20260813021506.55129-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the CPU declares AVX or AVX-512 support, verify that the corresponding xstate bits are also set. If not, warn and clear them. This eliminates the perceived need for AVX and AVX-512 optimized code in the kernel to call cpu_has_xfeatures(). That has never been universally done, which strongly suggests that it has never really been needed in practice, but this should remove any remaining doubt. Acked-by: Christoph Hellwig Signed-off-by: Eric Biggers --- arch/x86/kernel/fpu/xstate.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index a7b6524a9dea..97cfd4fb6cc0 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -806,7 +806,7 @@ static u64 __init guest_default_mask(void) void __init fpu__init_system_xstate(unsigned int legacy_size) { unsigned int eax, ebx, ecx, edx; - u64 xfeatures; + u64 xfeatures, mask; int err; int i; @@ -818,6 +818,8 @@ void __init fpu__init_system_xstate(unsigned int legacy_size) if (!boot_cpu_has(X86_FEATURE_XSAVE)) { pr_info("x86/fpu: x87 FPU will use %s\n", boot_cpu_has(X86_FEATURE_FXSR) ? "FXSAVE" : "FSAVE"); + /* Disable all dependent flags too */ + setup_clear_cpu_cap(X86_FEATURE_XSAVE); return; } @@ -833,7 +835,8 @@ void __init fpu__init_system_xstate(unsigned int legacy_size) cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx); fpu_kernel_cfg.max_features |= ecx + ((u64)edx << 32); - if ((fpu_kernel_cfg.max_features & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) { + mask = XFEATURE_MASK_FPSSE; + if ((fpu_kernel_cfg.max_features & mask) != mask) { /* * This indicates that something really unexpected happened * with the enumeration. Disable XSAVE and try to continue @@ -844,6 +847,24 @@ void __init fpu__init_system_xstate(unsigned int legacy_size) goto out_disable; } + mask |= XFEATURE_MASK_YMM; + if (boot_cpu_has(X86_FEATURE_AVX)) { + if ((fpu_kernel_cfg.max_features & mask) != mask) { + pr_err(FW_BUG + "x86/fpu: Disabling AVX support due to missing xstate features\n"); + setup_clear_cpu_cap(X86_FEATURE_AVX); + } + } + + mask |= XFEATURE_MASK_AVX512; + if (boot_cpu_has(X86_FEATURE_AVX512F)) { + if ((fpu_kernel_cfg.max_features & mask) != mask) { + pr_err(FW_BUG + "x86/fpu: Disabling AVX-512 support due to missing xstate features\n"); + setup_clear_cpu_cap(X86_FEATURE_AVX512F); + } + } + if (fpu_kernel_cfg.max_features & XFEATURE_MASK_APX && fpu_kernel_cfg.max_features & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) { /* -- 2.55.0