From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFFA93E1D13 for ; Thu, 13 Aug 2026 07:12:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=18.132.163.193 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786605140; cv=none; b=qrBgphq8hPdD4v1qJ4UPaCJmxQTGIzbYnbUatyLasbGLDTasJUsTfoFreyXiCIJtlzwG+bU8nCybuvVkLQuuPXRteI6y57ilPxd8Xj6qoHW7hR8jOp5q+YDW3A+UmOS6vOcIW0lUlMIG40G2MZ5oGkF1DfOwYkZft+m/I+HURVM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786605140; c=relaxed/simple; bh=V2DzkMjzGic606zBSHJ0FMRtI6tXr0c7HdmIxslpI/E=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=X0x1p871c5fPwH+iS/X8AdZsJ5L95+n5gIngh4Mr57wfqLtS4sIb2J3Q60/qTSpsaZYKWVBrZyOoHFs2zRpPe5IhK0VAAVSCGrZv1CaZjtdFGEEyws5mkImkHAtkBHPcCC/ZWmrbFg9jmUMMhYVx6v92fOZrazIgd5Qsqk0HdIw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=uniontech.com; spf=pass smtp.mailfrom=uniontech.com; dkim=pass (1024-bit key) header.d=uniontech.com header.i=@uniontech.com header.b=Fg4kcUCn; arc=none smtp.client-ip=18.132.163.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=uniontech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=uniontech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=uniontech.com header.i=@uniontech.com header.b="Fg4kcUCn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=uniontech.com; s=onoh2408; t=1786605112; bh=LExGksoYaR+hEaG6exOE3GIwFiO9/3wgLjqOrxxwjow=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Fg4kcUCnkvb8AiU/3OFQtGUe4/UKH5VVB14Fc3Xow4nnQo3YiMnOzirjBMF2AT3tL BJ8Cql/qYOPBO/CsVS/27Wmsr2pUw0T7MV6iQgJSD88H5aSFCgdmjB5tl54LxodQPZ 7m52U0n7xetpj6OFZOhGA6e1HNGDaqd1Mq8eXVQ4= X-QQ-mid: esmtpgz14t1786605105t14828269 X-QQ-Originating-IP: 6RJfcDlR2NFsZPkXLGNywnUvwH64IC2kVVkAFNBod/8= Received: from localhost.localdomain ( [1.85.7.34]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 13 Aug 2026 15:11:43 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 1 X-BIZMAIL-ID: 17309672441416219312 EX-QQ-RecipientCnt: 7 From: caina To: tglx@kernel.org Cc: maz@kernel.org, zouyipeng@huawei.com, majun258@huawei.com, guohanjun@huawei.com, linux-kernel@vger.kernel.org, kernel@uniontech.com Subject: mbigen: node 10+ interrupts lost after "Fix mbigen node address layout" Date: Thu, 13 Aug 2026 15:11:43 +0800 Message-Id: <20260813071143.15844-1-caina@uniontech.com> X-Mailer: git-send-email 2.20.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:uniontech.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: MDqtQ4jGWXAGLr+Y7cbwf+szYx0I3i2eyB2DJOShHDaqJoi10s1tUq9e q3sqWSxHD9CvMEHV9GSz67BuHTKivuQb2oII3Uoubvn4PcWlwRV4LtEmO7Puy7OQsEnbj7J Hvwjr0mzqd4/D7nCmBZkok88mYHErD8/8OtM8imH5q6vRyJzVTFKx3U02M6LpC9Pza7thZ5 BkqDlTODWAzUzfCKM4ycKskHrCxIhvem1bf9FC1s+mSwGtQxgGPqOlvpFkdVsCmxdyhn3NJ xpYPeIPTZKcBDynj5GGt6GQS5iKxELMVfwyu2HWa2/t1dbWGyI+TubCBqzmzHp/R7KriQaA z3EKPouTh0bHkg6PLNkZoUiybZGKz2B4cd/Pw5OfMLXbT9h7uIgz4zBkdw69JDGkeXLxRjI jeLQKWIEFzVyo2RvLwYvwdPaHv2BzxuCIkWHVivXu96Y0LnPwRzfjwXgGyMYDkcJ8gi0xAx ZzMChvTX8+vERT+5NS6SlpUO0DXaejUrbUc5kXnRzhRt9W2UmNyAK6Wx09Ye9WmH0JENPyv gLdD26jkPFo/TAFNpOea0GejsS3o4F2bQ2gMtVjQUWlcA9Y01/Gmi4L7cEY4SZ1pXzDOxgL OUtA7g/prL9OpqgdN5D0CxUOn2/x10CYXFOV2CR982Q+ACnbFH3PpJRIGX/DBdV8RCGHw6D UnVR3Bw8p8XKiBNE/dNf6U52pEOrFZzuaS0fHk8GtUUCKxQ3kPY1VSnhx9gRRKeWA5zYhGo Dxvb8+U78tlsofPkL988vrEq8qzJ5JqBDVqSSwFY/zjkgB8Fv36uR/XSCfpQqEeA7UPABpP 0UkrVNqE8gqUime1/7myaB40fgDjx++p1ublX4OSsW0eonVpBGWIaQ0bP9WT64Z6kJeJEFu 71GqZ/G/UANitoMnfxsKMKeGUV3F5HMaaD4tsSS3rrix+eNcGksZLt7rHGnppODK42m4zUD xp01gkFk5+9WuEmfr88pfh3q0QExBESVLVJuzfk3PRjhCl9r1pn9ZaDs1g/0uC2uAnsWIq7 bv4k3KeQ== X-QQ-XMRINFO: MPJ6Tf5t3I/ylTmHUqvI8+Wpn+Gzalws3A== X-QQ-RECHKSPAM: 0 Hi Thomas, Yipeng, Commit 6be6cba9c437 ("irqchip/mbigen: Fix mbigen node address layout") appears to cause a regression on Hi1616. Symptom ------- On-board hns NIC has two ports, enahisic2i0 and enahisic2i1, both behind mbigen-v2. Port 0 works; port 1 cannot pass any traffic. Their interrupt pins fall on different mbigen nodes: enahisic2i0: pins 1152-1198 → all in node 9 enahisic2i1: pins 1200-1246 → node 9 (1200-1215) + node 10 (1216-1246) (nid = (hwirq - 64) / 128 + 1; pin 1215 = node 9, pin 1216 = node 10) /proc/interrupts shows the break happens exactly at the node boundary: enahisic2i1-rx0 pin 1200 count 102 ← node 9 enahisic2i1-rx5 pin 1215 count 1 ← node 9, last pin enahisic2i1-tx5 pin 1216 count 0 ← node 10, first pin enahisic2i1-rx6 pin 1218 count 0 ← node 10 ...all node 10 pins stay at zero. Port 0 (entirely node 9) is unaffected. Reverting the commit restores normal operation. Why the commit's premise seems wrong ------------------------------------ The commit assumes CLEAR occupies a full 4 KB page at [0xa000, 0xb000) and collides with node 10, so node 10+ gets shifted by 0x1000. But get_mbigen_clear_reg() uses flat, chip-wide addressing — it never multiplies by the node ID: *addr = (hwirq / 32) * 4 + REG_MBIGEN_CLEAR_OFFSET; /* 0xa000 */ Over the valid hwirq range [64, 1407], CLEAR only spans 0xa008-0xa0af (168 bytes). Node 10's registers are: TYPE: 0xa000-0xa00f (16 B) overlaps CLEAR by 8 B (0xa008-0xa00f) VEC: 0xa200-0xa3ff (512 B) no overlap with CLEAR Shifting the whole page moves VEC from 0xa200 to 0xb200. The hardware reads the event ID from the fixed silicon address 0xa200 on interrupt firing, but software wrote it to 0xb200 — so the hardware gets an uninitialised value and the interrupt is lost. The only real overlap is 8 bytes of TYPE. It can only trigger when a single mbigen instance has devices on both node 1 (CLEAR 0xa008) and node 10 (TYPE 0xa008). On Hi1616 those nodes are on separate mbigen instances, so it never triggers. I don't have mbigen hardware documentation, so before sending a fix I'd like to understand whether the original commit was targeting a specific newer mbigen revision where CLEAR occupies a full 4 KB page. If so, the skip would need to be conditional on hardware revision rather than unconditional. If not, my inclination is to send a revert, or a narrower fix that skips CLEAR only in the TYPE path and leaves VEC untouched — the latter avoids the interrupt loss while still addressing the 8-byte TYPE/CLEAR overlap. Any insight into the target hardware would help me avoid breaking a platform I can't test. Thanks, caina