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Thu, 13 Aug 2026 02:39:34 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v4 16/27] vfio/cxl: Shadow the CXL DVSEC body at open Date: Thu, 13 Aug 2026 15:06:20 +0530 Message-ID: <20260813093631.2288172-17-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260813093631.2288172-1-mhonap@nvidia.com> References: <20260813093631.2288172-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468A:EE_|SAWPR12MB999318:EE_ X-MS-Office365-Filtering-Correlation-Id: 43193970-a912-4d65-ba06-08def91ed97a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|7416014|376014|1800799024|82310400026|921020|10067099003|11063799006|56012099006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MsjuFj2QFp7NQdN0tm57v8dKxco/dLjVW4ZkH5qJu5nJyxH4u8Re9TdsprpiWe+1BugyfANhYGtru0ueQO1KrSOERcqO4EYeP0zLQTv2K7Y1s1Kj2m9tKfDKWzXONOoOm5qEUKmsjBUz2nQairo1TWROnLVkMYy17HVKRAooSyykOS54w1MkjR6ktZpl8y6TgYZN2Je7dFQiBgzbsyyTdegqUBMVed96k4Z3UExc5tn68IIdSDPmiTCKQom6H56Fe5yZLo/1crnoYn0dW3a9q5ofVK7HriT75vglLFnhMHRvj3tI1vC2nox5rDSN05tyzB9O94IxDWWnrvoToWCRa4Oar4p4CnRnmVPQT+pRRbGdGxpe4cxDqNnvDAdl2YBCuO01882GpxN0MNXywwmRCtxzW/iIYoGQjCr/oHZ3E58q5GL1q1BnP1B9ozIaQRuA X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2026 09:40:02.4432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43193970-a912-4d65-ba06-08def91ed97a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAWPR12MB999318 From: Manish Honap Sample the CXL DVSEC body into a per-open shadow when the guest opens the device, and free it at close. Reading it here rather than at bind picks up any change from a low-power transition, and gives the DVSEC access handler added next a per-tenant copy to serve from. Annotate the shadow with __counted_by_ptr(dvsec_dwords) so its accesses are bounds-checked against the recorded dword count. Signed-off-by: Manish Honap --- drivers/vfio/pci/cxl/vfio_cxl_core.c | 39 ++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c index d19fd638f538..2e516a0929c6 100644 --- a/drivers/vfio/pci/cxl/vfio_cxl_core.c +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -17,11 +18,19 @@ * @cxlds: CXL device state; kept first for devm_cxl_dev_state_create() * @cxlmd: memory device joined to the CXL topology at bind * @hpa_range: host physical range of the HDM region + * @dvsec: CXL device DVSEC config-space offset + * @dvsec_len: length of the DVSEC body + * @dvsec_dwords: dword count of @dvsec_shadow + * @dvsec_shadow: guest view of the CXL DVSEC body, sampled at open */ struct vfio_cxl_state { struct cxl_dev_state cxlds; struct cxl_memdev *cxlmd; struct range hpa_range; + u16 dvsec; + u32 dvsec_len; + u32 dvsec_dwords; + u32 *dvsec_shadow __counted_by_ptr(dvsec_dwords); }; static int vfio_cxl_init_device(struct vfio_pci_core_device *vdev) @@ -71,6 +80,8 @@ static int vfio_cxl_init_device(struct vfio_pci_core_device *vdev) if (!cxl) return -ENOMEM; + cxl->dvsec = dvsec; + /* * vfio-pci requests the whole component BAR when the guest opens the * device. Declare the BAR owned so the CXL core maps the HDM/RAS @@ -102,11 +113,39 @@ static void vfio_cxl_release_device(struct vfio_pci_core_device *vdev) static int vfio_cxl_open_device(struct vfio_pci_core_device *vdev) { + struct vfio_cxl_state *cxl = vdev->cxl; + struct pci_dev *pdev = vdev->pdev; + u32 hdr, *shadow; + int i, dwords; + + /* + * Sample the DVSEC body now rather than at bind: a low-power + * transition could have changed it since the device was bound. + */ + pci_read_config_dword(pdev, cxl->dvsec + PCI_DVSEC_HEADER1, &hdr); + cxl->dvsec_len = PCI_DVSEC_HEADER1_LEN(hdr); + dwords = cxl->dvsec_len / sizeof(u32); + + shadow = kcalloc(dwords, sizeof(u32), GFP_KERNEL); + if (!shadow) + return -ENOMEM; + + for (i = 0; i < dwords; i++) + pci_read_config_dword(pdev, cxl->dvsec + i * sizeof(u32), + &shadow[i]); + + cxl->dvsec_dwords = dwords; + cxl->dvsec_shadow = shadow; + return 0; } static void vfio_cxl_close_device(struct vfio_pci_core_device *vdev) { + struct vfio_cxl_state *cxl = vdev->cxl; + + kfree(cxl->dvsec_shadow); + cxl->dvsec_shadow = NULL; } static const struct vfio_cxl_ops vfio_cxl_ops = { -- 2.25.1