Re: [PATCH] hw/sd/sdhci: complete non-interrupt ADMA descriptor chains in one pass

[Wadim Mueller <wafgo01@gmail.com>]

Hi Bin,

Thanks! I used the Icicle Kit as you suggested and posted the qtest as a
separate patch:

  [PATCH] tests/qtest: add Cadence SDHCI ADMA pacing/MMIO reproducer
  <https://lore.kernel.org/qemu-devel/20260813123210.28987-1-wafgo01@gmail.com/>

It drives the generic SDHCI model through the Cadence wrapper (SRS window
at 0x20008200) directly over MMIO under -accel qtest, and exercises two
facets against QEMU_CLOCK_VIRTUAL:

  - pacing: reports how many SDHC_TRANSFER_DELAY steps a non-interrupt
    ADMA2 chain takes to reach Transfer Complete;
  - MMIO coupling: after a chain that yields on a DMA-boundary interrupt
    descriptor, a bare interrupt-status read must not resume the pending
    transfer.

One caveat: the mmio-coupling case is written for the fixed behaviour --
it passes with your "Run ADMA independently of MMIO" (series 515264,
patch 12) applied and fails without it, so it is meant to land alongside
that change rather than on its own.

Happy to respin it or fold it into your series, whatever suits you best.

Thanks,
Wadim