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Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E7F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9510 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=mhonap@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.759, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org From: Manish Honap The SMMUv3 primary-bus check only accepted pxb-pcie as a valid extra root complex, so a CXL device behind a pxb-cxl could not reach the IOMMU: attaching an arm-smmuv3 to a pxb-cxl bus failed at realize with "SMMU should be attached to a default PCIe root complex (pcie.0) or a pxb-pcie based root complex". A pxb-cxl uses the same PCIe-compatible bus as a pxb-pcie, so accept it too. A CXL Type-2 device passed through with vfio-pci sits behind a pxb-cxl and needs SMMU translation for its DMA and ATS just like a pxb-pcie device. Signed-off-by: Manish Honap --- hw/arm/smmu-common.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 8e40ba603d..42fb098ab2 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -963,19 +963,20 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) s->iommu_ops = &smmu_ops; } /* - * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra - * root complexes to be associated with SMMU. + * We only allow the default PCIe root complex (pcie.0) or pxb-pcie / + * pxb-cxl based extra root complexes to be associated with SMMU. */ if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)) { /* - * This condition matches either the default pcie.0, pxb-pcie, or - * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set. - * Currently, we don't allow pxb-cxl as it requires further - * verification. Therefore, make sure this is indeed pxb-pcie. + * pcie.0 has no parent_dev; pxb-pcie and pxb-cxl do. Accept both bus + * types explicitly so other root complexes are still rejected. A + * pxb-cxl uses the same PCIe-compatible bus, so a CXL device behind it + * needs the SMMU just like a pxb-pcie one. */ if (pci_bus->parent_dev) { - if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) { + if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS) && + !object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_CXL_BUS)) { goto out_err; } } @@ -990,8 +991,8 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) return; } out_err: - error_setg(errp, "SMMU should be attached to a default PCIe root complex" - "(pcie.0) or a pxb-pcie based root complex"); + error_setg(errp, "SMMU should be attached to a default PCIe root complex " + "(pcie.0), a pxb-pcie, or a pxb-cxl based root complex"); } /* -- 2.25.1