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From: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: himal.prasad.ghimiray@intel.com,
	Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
Subject: [PATCH 4/6] drm/xe: dump GAM page fault report registers in devcoredump
Date: Thu, 13 Aug 2026 19:00:35 +0530	[thread overview]
Message-ID: <20260813133037.2912699-5-naresh.kumar.g@intel.com> (raw)
In-Reply-To: <20260813133037.2912699-1-naresh.kumar.g@intel.com>

Add PAGE_FLTRPTQ_HEAD_GAMCTRL and PAGE_FLTRPTQ_TAIL_GAMCTRL to the Xe
register definitions and capture them as part of the devcoredump
snapshot.

Include the register dump in the devcoredump output and release the
snapshot during cleanup so page fault report state is available for
post-mortem debugging.

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h      |  3 +++
 drivers/gpu/drm/xe/xe_devcoredump.c       | 25 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_devcoredump_types.h |  3 +++
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 959b1129fd50..25014bccd3a6 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -505,6 +505,9 @@
 #define   LMEM_EN				REG_BIT(31)
 #define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */
 
+#define PAGE_FLTRPTQ_HEAD_GAMCTRL		XE_REG(0xcf90)
+#define PAGE_FLTRPTQ_TAIL_GAMCTRL		XE_REG(0xcf94)
+
 #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
 #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
 
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index b339d4035628..6cc4e3969417 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -128,6 +128,11 @@ static const struct xe_reg_desc xe3p_media_gt_fuse_reglist[] = {
 	{ RPM_GCD_MEDIA, "RPM_GCD_MEDIA" },
 };
 
+static const struct xe_reg_desc xe3p_gam_pf_reglist[] = {
+	{ PAGE_FLTRPTQ_HEAD_GAMCTRL, "PAGE_FLTRPTQ_HEAD_GAMCTRL"},
+	{ PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"},
+};
+
 /**
  * struct xe_reg_desc_list - Struct for register descriptor list
  *
@@ -248,6 +253,19 @@ static struct xe_dbg_reg_snapshot *xe_media_gt_guc_reg_snapshot_capture(struct x
 	return xe_dbg_reg_snapshot_capture(gt, &reg_list);
 }
 
+static struct xe_dbg_reg_snapshot *xe_gam_pf_report_capture(struct xe_gt *gt)
+{
+	struct xe_reg_desc_list reg_list;
+
+	if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+		return NULL;
+
+	reg_list.regs = xe3p_gam_pf_reglist;
+	reg_list.num_regs = ARRAY_SIZE(xe3p_gam_pf_reglist);
+
+	return xe_dbg_reg_snapshot_capture(gt, &reg_list);
+}
+
 static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
 {
 	return container_of(coredump, struct xe_device, devcoredump);
@@ -308,6 +326,9 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
 	drm_puts(&p, "\n**** GuC CT ****\n");
 	xe_guc_ct_snapshot_print(ss->guc.ct, &p);
 
+	drm_printf(&p, "\n**** GAM PF Report ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->gam_pf_report);
+
 	drm_puts(&p, "\n**** Contexts ****\n");
 	xe_guc_exec_queue_snapshot_print(ss->ge, &p);
 
@@ -354,6 +375,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
 		xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
 	ss->matched_node = NULL;
 
+	xe_dbg_reg_snapshot_free(ss->gam_pf_report);
+	ss->gam_pf_report = NULL;
+
 	xe_guc_exec_queue_snapshot_free(ss->ge);
 	ss->ge = NULL;
 
@@ -557,6 +581,7 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
 	ss->media_gt_guc_reg = xe_media_gt_guc_reg_snapshot_capture(q->gt);
 	ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
 	ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
+	ss->gam_pf_report = xe_gam_pf_report_capture(q->gt);
 	ss->ge = xe_guc_exec_queue_snapshot_capture(q);
 	if (job)
 		ss->job = xe_sched_job_snapshot_capture(job);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 28b505176657..893eadd68a3d 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -86,6 +86,9 @@ struct xe_devcoredump_snapshot {
 		struct xe_guc_log_snapshot *log;
 	} guc;
 
+	/** @gam_pf_report: GAM PF report snapshot */
+	struct xe_dbg_reg_snapshot *gam_pf_report;
+
 	/** @ge: GuC Submission Engine snapshot */
 	struct xe_guc_submit_exec_queue_snapshot *ge;
 
-- 
2.43.0


  parent reply	other threads:[~2026-08-13 13:31 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-08-13 13:52   ` sashiko-bot
2026-08-13 13:30 ` [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
2026-08-13 14:04   ` sashiko-bot
2026-08-13 13:30 ` [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
2026-08-13 14:11   ` sashiko-bot
2026-08-13 13:30 ` Nareshkumar Gollakoti [this message]
2026-08-13 13:30 ` [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list Nareshkumar Gollakoti
2026-08-13 14:25   ` sashiko-bot
2026-08-13 13:30 ` [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
2026-08-13 14:37   ` sashiko-bot
2026-08-13 13:39 ` ✓ CI.KUnit: success for drm/xe: Capture additional HW register state " Patchwork
2026-08-13 14:27 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-13 15:58 ` ✗ Xe.CI.FULL: failure " Patchwork

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