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Thu, 13 Aug 2026 10:02:04 -0700 From: Besar Wicaksono To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , "Besar Wicaksono" Subject: [PATCH 1/2] perf vendor events arm64: fix swapped MetricGroup for Tegra410 L1 prefetcher metrics Date: Thu, 13 Aug 2026 17:01:54 +0000 Message-ID: <20260813170155.1156593-2-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260813170155.1156593-1-bwicaksono@nvidia.com> References: <20260813170155.1156593-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE5:EE_|SN7PR12MB7883:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fc53cd9-a6b8-4c11-b36f-08def95ca64f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|82310400026|36860700016|376014|7416014|10067099003|56012099006|6133799003|3023799007|11063799006|18002099003|22082099003|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: i2mmuEsBsx8fL4G/9Ltd+kphc7H8eBRLcZQ06+QzQZjhYC1ntqDjr+rDWlBtCFB9eE4DoXK0+uzcqU+iBgdSfZuU94m5Lo8gwS7WRV+mEvlVMYmvNPTP01tU5ls83xYnoUinFhIjtOzQu2KORPTdtJGl8hZEa6Qq4ljKafTVbwWz5nbiQ4H3zSeiMoNUfR8lp1STuDI+kLp/eLPWwtSvbwtEuIj0/hfdfmfyNlTK0NQip9hE3bpAMr+se8IlvxxC8peJ1hELarKYnJY2c3Sbv68vNv6+IYh3Gdb8muP9gxSACHivLBQAvTHYmcj/R7O3jV08q7z84iz5lmp3dvWJwg9U7euKwesabvRyqcwMgTtxyAUxsfagrO+JnunVICPYx0LdiQh9K8KGtt12CbBodPNj7vY+ZzodJY1eZ4QVGi09doSnzfKKBdCWcyy+5cxq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2026 17:02:25.5463 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fc53cd9-a6b8-4c11-b36f-08def95ca64f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7883 From: Saurav Sachidanand The L1D prefetcher metrics (l1d_cache_rw_miss_ratio, l1d_demand_accesses, etc.) were incorrectly assigned to MetricGroup "L1I_Prefetcher_Effectiveness" and vice versa. This causes 'perf stat --metric-group L1D_Prefetcher_Effectiveness' to display L1I metrics, which is misleading. Swap the MetricGroup assignments so L1D metrics are in the L1D group and L1I metrics are in the L1I group. Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events") Signed-off-by: Saurav Sachidanand Reviewed-by: Besar Wicaksono --- .../arch/arm64/nvidia/t410/metrics.json | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json index b825ede03f54..59474ccb7417 100644 --- a/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json @@ -346,42 +346,42 @@ "MetricExpr": "l1d_demand_misses / l1d_demand_accesses", "BriefDescription": "This metric measures the ratio of L1 D-cache Read accesses missed to the total number of L1 D-cache accesses. This gives an indication of the effectiveness of the L1 D-cache for demand Load or Store traffic.", "ScaleUnit": "1per cache access", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_demand_accesses", "MetricExpr": "L1D_CACHE_RW", "BriefDescription": "This metric measures the count of L1 D-cache accesses incurred on Load or Store by the instruction stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_demand_misses", "MetricExpr": "L1D_CACHE_REFILL_RW", "BriefDescription": "This metric measures the count of L1 D-cache misses incurred on a Load or Store by the instruction stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_prf_accuracy", "MetricExpr": "100 * (l1d_useful_prf / l1d_refilled_prf)", "BriefDescription": "This metric measures the fraction of prefetched memory addresses that are used by the instruction stream.", "ScaleUnit": "1percent of prefetch", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_prf_coverage", "MetricExpr": "100 * (l1d_useful_prf / (l1d_demand_misses + l1d_refilled_prf))", "BriefDescription": "This metric measures the baseline demand cache misses which the prefetcher brings into the cache.", "ScaleUnit": "1percent of cache access", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_refilled_prf", "MetricExpr": "L1D_CACHE_REFILL_HWPRF + L1D_CACHE_REFILL_PRFM + L1D_LFB_HIT_RW_FHWPRF + L1D_LFB_HIT_RW_FPRFM", "BriefDescription": "This metric measures the count of cache lines refilled by L1 data prefetcher (hardware prefetches or software preload) into L1 D-cache.", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1d_tlb_miss_ratio", @@ -402,7 +402,7 @@ "MetricExpr": "L1D_CACHE_HIT_RW_FPRF + L1D_LFB_HIT_RW_FHWPRF + L1D_LFB_HIT_RW_FPRFM", "BriefDescription": "This metric measures the count of cache lines refilled by L1 data prefetcher (hardware prefetches or software preload) into L1 D-cache which are further used by Load or Store from the instruction stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1I_Prefetcher_Effectiveness" + "MetricGroup": "L1D_Prefetcher_Effectiveness" }, { "MetricName": "l1i_cache_miss_ratio", @@ -423,42 +423,42 @@ "MetricExpr": "l1i_demand_misses / l1i_demand_accesses", "BriefDescription": "This metric measures the ratio of L1 I-cache Read accesses missed to the total number of L1 I-cache accesses. This gives an indication of the effectiveness of the L1 I-cache for demand instruction fetch traffic. Note that cache accesses in this cache are demand instruction fetch.", "ScaleUnit": "1per cache access", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_demand_accesses", "MetricExpr": "L1I_CACHE_RD", "BriefDescription": "This metric measures the count of L1 I-cache accesses caused by an instruction fetch by the instruction stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_demand_misses", "MetricExpr": "L1I_CACHE_REFILL_RD", "BriefDescription": "This metric measures the count of L1 I-cache misses caused by an instruction fetch by the instruction stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_prf_accuracy", "MetricExpr": "100 * (l1i_useful_prf / l1i_refilled_prf)", "BriefDescription": "This metric measures the fraction of prefetched memory addresses that are used by the instruction stream.", "ScaleUnit": "1percent of prefetch", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_prf_coverage", "MetricExpr": "100 * (l1i_useful_prf / (l1i_demand_misses + l1i_refilled_prf))", "BriefDescription": "This metric measures the baseline demand cache misses which the prefetcher brings into the cache.", "ScaleUnit": "1percent of cache access", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_refilled_prf", "MetricExpr": "L1I_CACHE_REFILL_HWPRF + L1I_CACHE_REFILL_PRFM", "BriefDescription": "This metric measures the count of cache lines refilled by L1 instruction prefetcher (hardware prefetches or software preload) into L1 I-cache.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l1i_tlb_miss_ratio", @@ -479,7 +479,7 @@ "MetricExpr": "L1I_CACHE_HIT_RD_FPRF", "BriefDescription": "This metric measures the count of cache lines refilled by L1 instruction prefetcher (hardware prefetches or software preload) into L1 I-cache which are further used by instruction stream of the program.", "ScaleUnit": "1count", - "MetricGroup": "L1D_Prefetcher_Effectiveness" + "MetricGroup": "L1I_Prefetcher_Effectiveness" }, { "MetricName": "l2_cache_miss_ratio", -- 2.43.0