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From: sashiko-bot@kernel.org
To: "Aiden Isik" <aidenisik@member.fsf.org>
Cc: linux-clk@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309
Date: Mon, 17 Aug 2026 10:37:11 +0000	[thread overview]
Message-ID: <20260817103711.943D81F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260817-for-next-lucky7-clock-v1-2-032e4b229c76@member.fsf.org>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Logic Error / Out-of-bounds Read when rate_table is empty
- [Medium] Single-Responsibility Violation: Undocumented architectural refactoring
--

--- Patch [2]: [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309 ---
commit d62df56ff2e6bf73437e6e25e1335b3fb4571268
Author: Aiden Isik <aidenisik@member.fsf.org>

clk: samsung: clk-pll: Add support for pll_309

This commit adds support for the pll_309 used in the Exynos5515 SoC, defining
the PLL characteristics which are handled similarly to pll_531x.

> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index e74552846ba34..8b1474aeaf0c8 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -1593,32 +1593,35 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>  {
>  	struct samsung_clk_pll *pll;
>  	struct clk_init_data init;
> -	unsigned int len = 0;
> -	int ret;
> +	int ret, len;
>  
> -	if (pll_clk->rate_table) {
> -		/* find count of rates in rate_table */
> -		while (pll_clk->rate_table[len].rate != 0)
> -			len++;
> -	}
> -
> -	pll = kzalloc_flex(*pll, rate_table, len);
> +	pll = kzalloc_obj(*pll);

[Severity: Medium]
This isn't a bug, but the commit message only mentions adding support for the
new pll_309 type, while this code changes the allocation semantics of the
rate_table across the entire driver, switching from a flexible array member
to a separate pointer allocation. 

Could this architectural refactoring be split into a separate patch or
documented in the commit message?

[ ... ]

> @@ -1637,7 +1640,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>  	case pll_a9fracm:
>  		pll->enable_offs = PLL35XX_ENABLE_SHIFT;
>  		pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
> -		if (!pll->rate_count)
> +		if (!pll->rate_table)

[Severity: High]
If a clock is registered with an empty rate table containing only the zero
terminator, kmemdup_array() is called with a count of 0 earlier in this
function and returns ZERO_SIZE_PTR rather than NULL.

Since ZERO_SIZE_PTR is not NULL, this check evaluates to false, which
incorrectly assigns the full operations instead of the safe min_ops fallback.

If samsung_pll_determine_rate() is subsequently called, it skips its loop
because rate_count is 0, and attempts to access rate_table[-1]:

samsung_pll_determine_rate() {
    ...
    req->rate = rate_table[i - 1].rate;
}

Since rate_table is ZERO_SIZE_PTR, will this result in an out-of-bounds
memory read?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260817-for-next-lucky7-clock-v1-0-032e4b229c76@member.fsf.org?part=2

  reply	other threads:[~2026-08-17 10:37 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-17 10:17 [PATCH 0/3] clk: samsung: Introduce Exynos5515 clock driver support Aiden Isik via B4 Relay
2026-08-17 10:17 ` Aiden Isik
2026-08-17 10:17 ` [PATCH 1/3] dt-bindings: clock: Add Exynos5515 SoC Aiden Isik via B4 Relay
2026-08-17 10:17   ` Aiden Isik
2026-08-17 10:17 ` [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309 Aiden Isik via B4 Relay
2026-08-17 10:17   ` Aiden Isik
2026-08-17 10:37   ` sashiko-bot [this message]
2026-08-17 11:47     ` Aiden Isik
2026-08-17 10:17 ` [PATCH 3/3] clk: samsung: Introduce Exynos5515 clock driver Aiden Isik via B4 Relay
2026-08-17 10:17   ` Aiden Isik
2026-08-17 10:27   ` sashiko-bot
2026-08-17 11:12     ` Aiden Isik

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