From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A36953E95AB; Mon, 17 Aug 2026 13:41:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786974120; cv=none; b=IYWNYSJ1hOE5dY/46Ia48UdljgnFZ1xzkKt0o/iKC1T9QOQlJH2vS2YlCAYNMUvUbpMA4a9GdXWCnEgBtHCsH96Od2zaW7PjcqnAIWG54mW43v5HRs+61muS4DsM0Fr4MC1tNb2Mnkoz7SyasfB9sxrDxepG7qIXw3tSXof4tyo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786974120; c=relaxed/simple; bh=BUDWEG+6/U+MPVuEtRQWpaxYuQYIGjfdtgis0aWXfGM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tGc4Jq/vmsycIlEUH3Drdx2YP4F8eG81JlABe1UrEc8BqNJ8mvCf34sgxJYQ3Z0WZutBekj1rscCf1L+7YMPRD3Y2bL/kEXQfd4ALNBleXZ4KHa7mpRJ606WPy+yf17B1wnNe51Fk/sL1FFHLJeraQ2oRrz+XGoSOjVY2AIqRk0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=uxCpUeCt; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="uxCpUeCt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 455031F000E9; Mon, 17 Aug 2026 13:41:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1786974117; bh=aCmpAypGoXNkahBD7W7I2y3RKmCvmoedv5GO5AHM1Zc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=uxCpUeCtbSdPlts3TbiO2pbO8ZU0Pf7ihgDtOOg1p3UdVDdPrGPgLVktmLhqHx9bp F4F0FVuCK12vgQPHUB3rG/goO7kFg9Y80/xq0+PVWLKhtZwKvqG5yN+4BQgEaDYjU2 efSKuX15QyCWGpnZFC3QQ0qj0zy+wsdTMd3zoTDA= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Pavan Chebbi , Kalesh AP , Michael Chan , Jakub Kicinski , Sasha Levin Subject: [PATCH 7.1 096/271] bnxt_en: Disable EOP for TPA on all chips to prevent data corruption Date: Mon, 17 Aug 2026 15:30:21 +0200 Message-ID: <20260817132540.738517538@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260817132536.752504388@linuxfoundation.org> References: <20260817132536.752504388@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Michael Chan [ Upstream commit c3faf548a00f4c17100cc9204746975fa46a73b9 ] EOP (End of frame padding) on the AGG ring may cause overlapping of zero padding at the end of one segment with the next segment's data. If Relaxed Ordering (RO) is enabled, the zero padding may overwrite valid data in the next segment and corrupt the data. Older chips (P5 and older) do not automatically disable RO when EOP is enabled. On some ARM systems, data corruption was reported on 57508 (P5) chips with RO enabled. Always disable EOP on all chips on the AGG rings when TPA is enabled to fix the data corruption. Fixes: bfcd8d791ec1 ("bnxt_en: Add fast path logic for TPA on 57500 chips.") Reviewed-by: Pavan Chebbi Reviewed-by: Kalesh AP Signed-off-by: Michael Chan Link: https://patch.msgid.link/20260731190937.807270-5-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index e7145537f3e73..1cd6e88d4e814 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -4611,11 +4611,14 @@ static void bnxt_init_one_rx_agg_ring_rxbd(struct bnxt *bp, type = ((u32)rxr->rx_page_size << RX_BD_LEN_SHIFT) | RX_BD_TYPE_RX_AGG_BD; - /* On P7, setting EOP will cause the chip to disable - * Relaxed Ordering (RO) for TPA data. Disable EOP for - * potentially higher performance with RO. + /* Disable EOP if TPA is enabled to prevent overlapping zero + * padding with the next segment's data. On P7_PLUS, EOP will + * automatically disable Relaxed Ordering (RO) to prevent + * potential data corruption (and may degrade performance). On + * older chips, RO will not be automatically disabled and may + * cause corruption. */ - if (BNXT_CHIP_P5_AND_MINUS(bp) || !(bp->flags & BNXT_FLAG_TPA)) + if (!(bp->flags & BNXT_FLAG_TPA)) type |= RX_BD_FLAGS_AGG_EOP; bnxt_init_rxbd_pages(ring, type); -- 2.53.0