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From: Vladimir Isaev <vvisaev@gmail.com>
To: qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,
	zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com,
	qemu-riscv@nongnu.org, joel@jms.id.au, npiggin@gmail.com,
	Vladimir Isaev <vvisaev@gmail.com>
Subject: [PATCH v2 0/2] Fix alignment check for misa write
Date: Mon, 17 Aug 2026 18:06:36 +0300	[thread overview]
Message-ID: <20260817150653.40357-1-vvisaev@gmail.com> (raw)

Current version disable misa.C on misa write when next instruciton is
not aligned, fix it and add test.

Changes from v1:
  - Use the test from https://lore.kernel.org/r/20260321144554.606417-2-npiggin@gmail.com,
    since it is much more comprehensive than mine.
  - Add GUEST_ERROR_LOG on a bad write attempt.

Vladimir Isaev (2):
  riscv: csr: do not drop C bit on misa write
  tests/tcg/riscv64: add misa write test

 target/riscv/tcg/csr.c                    | 10 ++-
 tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
 tests/tcg/riscv64/test-misa-w.S           | 88 +++++++++++++++++++++++
 3 files changed, 99 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-misa-w.S

-- 
2.55.0



             reply	other threads:[~2026-08-17 15:07 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-17 15:06 Vladimir Isaev [this message]
2026-08-17 15:06 ` [PATCH v2 1/2] riscv: csr: do not drop C bit on misa write Vladimir Isaev
2026-08-17 15:06 ` [PATCH v2 2/2] tests/tcg/riscv64: add misa write test Vladimir Isaev

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