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Tue, 18 Aug 2026 18:05:32 -0700 (PDT) Received: from Turin ([187.15.143.241]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90c5f29065bsm2398716d6.24.2026.08.18.18.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 18:05:31 -0700 (PDT) From: Nicholas Dudar To: bpf@vger.kernel.org Cc: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, johan.almbladh@anyfinetworks.com, paulburton@kernel.org, tsbogend@alpha.franken.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC bpf-next 0/2] bpf, mips: Add BPF_MOVSX support to the JITs Date: Tue, 18 Aug 2026 21:05:21 -0400 Message-ID: <20260819010523.1057789-1-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit bpf-next is closed for the merge window, so I am sending this for review. I plan to post this series after it reopens. The MIPS32 and MIPS64 JITs lower register BPF_MOVSX as an ordinary move because their register-move paths do not interpret insn->off. Negative low-width values therefore retain incorrect upper bits. First factor ordinary register moves into backend-local 32- and 64-bit helpers. Then handle the BPF-defined MOVSX widths from insn->off in those helpers. This keeps the verifier-inserted ALU32 zero extension on its existing path and preserves the MIPS32 register-pair handling. The implementation uses shift sequences rather than the R2+ seb/seh instructions so it also works on base MIPS32. MOVSX can be applied before or after the in-flight SDIV/SMOD series. Both must precede MEMSX (yet to be sent). The ordering discussion is here: Link: https://lore.kernel.org/bpf/CAJZwKkis=3NGw9At0WfiZaRYEoMPbQfqJKN0e+vtRDvp4VY5Ng@mail.gmail.com/ Patch 1 did not change any test_bpf result. On the four little-endian profiles where the complete suite was run at each boundary, patch 2 fixed the ALU32 byte and halfword MOVSX cases and the ALU64 byte, halfword, and word cases. The 32-bit totals moved from 1031 passes and 31 failures to 1036 passes and 26 failures; the 64-bit totals moved from 1030 passes and 31 failures to 1035 passes and 26 failures. Patch 2 did not change any other test result. Ordinary MOV and zero-extension controls passed at each boundary. Selector-focused QEMU testing covered MIPS32 base, R2, and R6 plus pre-R6 MIPS64, each in big- and little-endian configurations. No physical MIPS hardware was tested. Nicholas Dudar (2): bpf, mips: Factor register moves into helpers bpf, mips: Add support for BPF_MOVSX in the JITs arch/mips/net/bpf_jit_comp32.c | 54 +++++++++++++++++++++++++++++++--- arch/mips/net/bpf_jit_comp64.c | 48 ++++++++++++++++++++++++++++-- 2 files changed, 95 insertions(+), 7 deletions(-) base-commit: 6655c409707ec8ce9ce0850ffe4fe02331fd4d9c